WIN Enterprises MB-73440 User Manual Download Page 70

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MB-73440

Scaling Off

Force Scaling

panel scaling

option used by

the Internal

Graphics Device.

Backlight

Control

PWM Inverted

PWM Normal

Back Light

Control Setting.

Active

LFP

Disabled

Enabled

Configuring LFP

usage

Panel

Color

Depth

18 Bit

24 Bit

Select the LFP

Panel Color

Depth

Feature

Options

Description

PEG Port

Configuration

Info only

PEG 0:1:0

Not

Present

Display PEG0 present or not.

Enable Root Port

Disabled

Enabled

Auto

Enable or Disable the Root Port.

Max Link Speed

Auto

Gen1

Gen2

Gen3

Configure PEG 0:1:0 Max Speed

PEG 0:1:1

Not

Present

Display PEG1 present or not.

Enable Root Port

Disabled

Enabled

Auto

Enable or Disable the Root Port.

Max Link Speed

Auto

Gen1

Gen2

Gen3

Configure PEG 0:1:1 Max Speed

PEG 0:1:2

Not

Present

Display PEG2 present or not.

PEG Port Configuration Submenu

Enable Root Port

Disabled

Enabled

Auto

Enable or Disable the Root Port.

Summary of Contents for MB-73440

Page 1: ...WIN Enterprises Inc Custom Embedded Solutions COM Express MB 73440 User s Manual ...

Page 2: ...Copyright WIN Enterprises Inc MB 73440 2 Version Release Date Part Number ...

Page 3: ...Copyright WIN Enterprises Inc MB 73440 1 Revision History Revision Description Date By 1 0 Initial Release 2016 5 23 T C ...

Page 4: ...nformation listed in this user manual including but not limited to product specifications or drawings is subject to change without prior notice WIN Enterprises Inc provides no warranty in any form with regard to this document and information contained herein and hereby expressly disclaims any expressed or implied warranties of merchantability or fitness for any particular purpose with regard to an...

Page 5: ...ed accordingly In any case this product can not be opened handled stored or transported without proper ESD protection mechanisms and please store and ship this product in its original manufacturer s packaging Failure to comply with these guidelines will make this product damaged and avoid Limited Warranty offered by WIN Enterprises Inc ...

Page 6: ...3 2 9 Debug Headers 13 2 10 Power Specifications 13 2 11 Environmental Requirements 13 2 12 Regulatory Compliance 14 2 13 Operating Systems 14 2 14 Functional Diagram 15 3 Mechanical Information 16 3 1 Mechanical Dimensions 16 3 2 Module Connector 18 3 3 Thermal Solution for reference only 19 3 3 1 Heat Sink 19 3 3 2 Installation 19 3 4 Mounting Methods 22 3 4 1 Mechanical Specification 22 4 Pinou...

Page 7: ...s Connector C D 46 4 5 1 USB 3 0 Extension 46 4 5 2 PCI Express x1 46 4 5 3 DDI Channels 47 4 5 4 DDI to DP HDMI SDVO Mapping 49 4 5 5 Module Type Definition 50 4 5 6 Power and Ground 51 5 System Resources 52 5 1 System Memory Map 52 5 2 I O Map 52 5 3 Interrupt Request IRQ Lines 53 5 3 1 PIC Mode 53 5 3 2 APIC Mode 54 5 4 PCI Configuration Space Map 55 5 5 PCI Interrupt Routing Map 56 5 6 SMBus A...

Page 8: ...Configuration 65 6 2 11 System Agent SA Configuration 66 6 2 12 PCH IO Configuration 69 6 3 Boot 71 6 4 Security 71 6 5 Save Exit 71 7 BIOS Checkpoints Beep Codes 73 7 1 Status Code Ranges 73 7 2 Standard Status Codes 73 7 2 1 SEC Status Codes 73 7 2 2 SEC Beep Codes 74 7 2 3 PEI Status Codes 74 7 2 4 PEI Beep Codes 76 7 2 5 DXE Status Codes 76 7 2 6 DXE Beep Codes 79 7 2 7 ACPI ASL Checkpoint 79 ...

Page 9: ...ard s Intel processors support Intel Hyper Threading Technology up to 2 cores 4 threads and up to 32 GB of non ECC DDR4 dual channel memory at 1866 2133 MHz in dual stacked SODIMM sockets to provide excellent overall performance Integrated Intel Generation 9 Low Power Graphics includes features such as OpenGL 4 4 4 3 DirectX 11 3 11 Intel Clear Video HD Technology Advanced Scheduler 2 0 1 0 XPDM s...

Page 10: ...prises Inc MB 73440 8 PCI N A 32 bit N A N A IDE Channel 1 1 LAN port 1 1 1 1 USB 2 0 USB 3 0 8 0 8 0 8 4 8 0 Display Interfaces VGA LVDS VGA LVDS PEG SDVO VGA LVDS PEG 3 X DDI 1x DDI 1 1 Hardware Briefing 1 1 1 TOP VIEW ...

Page 11: ...Copyright WIN Enterprises Inc MB 73440 9 1 Mounting holes 2 SODIMMDDR4 slot 3 Port 80 4 XDP Debug Header 5 SATA SSD 6 SkyLake U 7 BIOS 1 1 2 BOTTOM VIEW ...

Page 12: ... cTDP support 2C GT2 Intel Core i3 6100U 2 3 GHz no Turbo 15W cTDP support 2C GT2 CPU Supported Intel VT Intel Turbo Boost Technology 2 0 Intel TXT Intel AVX2 Intel SSE4 2 Intel AES NI Intel HT Technology Intel PCLMULQDQ Instruction Intel 64 Architecture Intel Device Protection Technology with Intel Secure Key Intel Execute Disable Bit Intel TSXNI Note Availability of features may vary between pro...

Page 13: ...x4 x2 x1 LPC bus X1 SMBus system X1 2 3 Video GPU Intel Generation 9 Graphics integrated in CPU and featured with Supports 3 displays independently simultaneously via Display Port HDMI LVDS monitors eDP optional in place of LVDS Encode transcode high definition HD video supported High definition HD video e g Blu ray DVD supported Playback of Blu ray Disc 3D content via HDMI HDMI e1 4a DirectX Vide...

Page 14: ...XP IC via eDP to LVDS chip eDP 4 lanes supported maximum integrated in LVDS BOM optional Digital Display Port x 2 DisplayPort HDMI DVI supported 2 4 Audio Intel HD Audio integrated on SoC Audio Codec Integrated in AW COMe EVAL carrier board 2 5 LAN Intel PHY Intel Ethernet Controller i219LM Interface 10 100 1000 GbE connection 2 6 Multi I O and Storage USB 4x USB 3 0 USB 1 2 3 8x USB 2 0 USB 0 1 2...

Page 15: ...r for ICE debug of CPU chipset optional 2 10 Power Specifications Power Modes AT and ATX mode Standard Voltage Input ATX 12V 5 5Vsb 5 AT 12V 5 Wide Voltage Input ATX 5 20 V 5Vsb 5 AT 5 20V Power Management ACPI 5 0 compliant Power States supports C1 C6 S0 S3 S4 S5 Wake on USB S3 WoL S3 S4 S5 Power Consumption For information about power consumption please contacts our business representative 2 11 ...

Page 16: ...zardous Substance free RoHS Compliant This product is designed and developed on hazardous substance free components and parts and totally RoHS Restriction of Hazardous Substances Directive 2002 95 EC compliant 2 13 Operating Systems MB 73440 board supports following operating systems Red Hat Enterprise 6 4 Fedora 20 Microsoft Windows 7 Ultimate 64 bit Microsoft Windows 8 1 Professional 64 bit Wind...

Page 17: ...Copyright WIN Enterprises Inc MB 73440 15 2 14 Functional Diagram ...

Page 18: ...Copyright WIN Enterprises Inc MB 73440 16 3 Mechanical Information 3 1 Mechanical Dimensions Unit mm ...

Page 19: ...Copyright WIN Enterprises Inc MB 73440 17 Unit mm ...

Page 20: ...18490 6 220 pin board to board connector with 0 5mm for a stacking height of 8 mm This connector can be used with 8 mm through hole standoffs SMT type Common Specifications Current capacity 0 5A per pin Rated voltage 50 VAC Insulation resistance 100M or greater 500 VDC Temperature rating 40 C 85 C UL certification ECBT2 E28476 Copper alloy contacts Housing thermo plastic molded compound L C P ...

Page 21: ...s below are based on heat sink as an example 3 3 2 Installation Prepare parts below Heatsink assembly X 1 COM Express Carrier board X 1 MB COMe EVAL Fastening screws M2 5 L 8 mm X 2 Fastening screws M2 5 L 16 mm X 5 Step 1 Remove the protective film from the thermal pads Step 2 Align the mounting holes of the module fit the module onto the heat thing by securing the two fastening screws M2 5 L 8 m...

Page 22: ... and align the three studs of the module to the three studs of the carrier board b Fit the heat sink assembly with the module by pressing where the arrow indicates c Lay down the heat sink assembly with the module Step 4 Tighten the shipped five fastening screws M2 5 L 16 mm to secure the module ...

Page 23: ...Copyright WIN Enterprises Inc MB 73440 21 Step 5 Connect the power plug of the heat sink assembly ...

Page 24: ...r the heat spreader by itself does not constitute the complete thermal solution for a Module but provides a common interface between Modules and implementation specific thermal solutions If implemented a heat spreader for the Basic form factor shall use an implementation specific set of holes and spacers to attach the heat spreader to the Module These implementation specific holes are ...

Page 25: ...r combination to the Carrier Board An independent implementation specific set of holes and spacers shall be used to attach the heat spreader to the Module Unit mm Tolerances shall be 0 25mm 0 010 unless noted otherwise The 440 pin connector pair shall be mounted on the backside of the PCB and is seen through the board in this view The four mounting holes shown shall use 6mm diameter pads and shall...

Page 26: ...pact the Basic and the Extended Modules The Module PCB and heat spreader plate thickness are vendor implementation specific however a 2 mm PCB with a 3 mm heat spreader may be used which allows use of readily available standoffs Tolerances unless otherwise specified Z height dimensions should be 0 8mm 0 031 from top of Carrier Board to top of heatspreader Heat spreader surface should be flat withi...

Page 27: ...Copyright WIN Enterprises Inc MB 73440 25 ...

Page 28: ... 1 Connector A B PIN Row A PIN Row B A1 GND FIXED B1 GND FIXED A2 GBE0_MDI3 B2 GBE0_ACT A3 GBE0_MDI3 B3 LPC_FRAME A4 GBE0_LINK100 B4 LPC_AD0 A5 GBE0_LINK1000 B5 LPC_AD1 A6 GBE0_MDI2 B6 LPC_AD2 A7 GBE0_MDI2 B7 LPC_AD3 A8 GBE0_LINK B8 LPC_DRQ0 A9 GBE0_MDI1 B9 LPC_DRQ1 ...

Page 29: ...XED A22 SATA2_TX B22 SATA3_TX A23 SATA2_TX B23 SATA3_TX A24 SUS_S5 B24 PWR_OK A25 SATA2_RX B25 SATA3_RX A26 SATA2_RX B26 SATA3_RX A27 BATLOW B27 WDT A28 S ATA_ACT B28 AC HDA_SDIN2 A29 AC HDA_SYNC B29 AC HDA_SDIN1 A30 AC HDA_RST B30 AC HDA_SDIN0 A31 GND FIXED B31 GND FIXED A32 AC HDA_BITCLK B32 SPKR A33 AC HDA_SDOUT B33 I2C_CK A34 BIOS_DIS0 B34 I2C_DAT A35 THRMTRIP B35 THRM A36 USB6 B36 USB7 A37 US...

Page 30: ...PCIE_RX3 A59 PCIE_TX3 B59 PCIE_RX3 A60 GND FIXED B60 GND FIXED A61 PCIE_TX2 B61 PCIE_RX2 A62 PCIE_TX2 B62 PCIE_RX2 A63 GPI1 SD_DATA1 B63 GPO3 SD_CD A64 PCIE_TX1 B64 PCIE_RX1 A65 PCIE_TX1 B65 PCIE_RX1 A66 GND B66 WAKE0 A67 GPI2 SD_DATA2 B67 WAKE1 A68 PCIE_TX0 B68 PCIE_RX0 A69 PCIE_TX0 B69 PCIE_RX0 A70 GND FIXED B70 GND FIXED A71 LVDS_A0 eDP_TX2 B71 LVDS_B0 A72 LVDS_A0 eDP_TX2 B72 LVDS_B0 A73 LVDS_A...

Page 31: ...ED A90 GND FIXED B90 GND FIXED A91 SPI_POWER B91 VGA_GRN A92 SPI_MISO B92 VGA_BLU A93 GPO0 SD_CLK B93 VGA_HSYNC A94 SPI_CLK B94 VGA_VSYNC A95 SPI_MOSI B95 VGA_I2C_CK A96 TPM_PP B96 VGA_I2C_DAT A97 TYPE10 B97 SPI_CS A98 SER0_TX B98 RSVD A99 SER0_RX B99 RSVD A100 GND FIXED B100 GND FIXED A101 SER1_TX CAN_TX B101 FAN_PWMOUT A102 SER1_RX CAN_RX B102 FAN_TACHIN A103 LID B103 SLEEP A104 VCC_12V B104 VCC...

Page 32: ... GND FIXED C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX C17 RSVD D17 RSVD C18 RSVD D18 RSVD C19 PCIE_RX6 D19 PCIE_TX6 C20 PCIE_RX6 D20 PCIE_TX6 C21 GND FIXED D21 GND FIXED C22 PCIE_RX7 D22 PCIE_TX7 C23 PCIE_RX7 D23 PCIE_TX7 C24 DDI1_HPD D24 RSVD C25 DDI1_PAIR4 D25 RSVD C26 DDI1_PAIR4 D26 DDI1_PAIR0 C27 RSVD D27 DDI1_PAIR0 C28 RSVD D28 RSVD C29 DDI1_PAIR5 D29 DDI1_PAIR1 ...

Page 33: ...AIR2 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C48 RSVD D48 RSVD C49 DDI3_PAIR3 D49 DDI2_PAIR3 C50 DDI3_PAIR3 D50 DDI2_PAIR3 C51 GND FIXED D51 GND FIXED C52 PEG_RX0 D52 PEG_TX0 C53 PEG_RX0 D53 PEG_TX0 C54 TYPE0 D54 PEG_LANE_RV C55 PEG_RX1 D55 PEG_TX1 C56 PEG_RX1 D56 PEG_TX1 C57 TYPE1 D57 TYPE2 C58 PEG_RX2 D58 PEG_TX2 C59 PEG_RX2 D59 PEG_TX2 C60 GND FIXED D60 GND FIXED C61 PEG_RX3 D61 PEG_TX3 C62 PEG_RX3 D62 P...

Page 34: ... C84 GND D84 GND C85 PEG_RX10 D85 PEG_TX10 C86 PEG_RX10 D86 PEG_TX10 C87 GND D87 GND C88 PEG_RX11 D88 PEG_TX11 C89 PEG_RX11 D89 PEG_TX11 C90 GND FIXED D90 GND FIXED C91 PEG_RX12 D91 PEG_TX12 C92 PEG_RX12 D92 PEG_TX12 C93 GND FIXED D93 GND FIXED C94 PEG_RX13 D94 PEG_TX13 C95 PEG_RX13 D95 PEG_TX13 C96 GND FIXED D96 GND FIXED C97 RSVD D97 RSVD C98 PEG_RX14 D98 PEG_TX14 C99 PEG_RX14 D99 PEG_TX14 C100 ...

Page 35: ... 3 3V tolerant I 5V Input 5V tolerant O 3 3V 3 3V output signal O 5V 5V output signal I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference voltage output that may be sourced from a module power plane PDS Pull down strap This is an output pin on the module that is either tied t...

Page 36: ... designed to drive a 37 5Ω equivalent load O Analog not supported VGA_GRN B91 Green for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog not supported VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog not supported VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3 3V not supported VGA_VSYNC B94 Vertical sync ou...

Page 37: ...10K LVDS_BKLT_EN B79 LVDS panel backlight enable O 3 3V PD 10K Note eDP support is a BOM option LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3 3V PD 100K ePD to LVDS requirement LVDS_I2C_CK A83 DDC lines used for flat panel detection and control O 3 3V PU 2k2 3 3V LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control I O 3 3V PU 2k2 3 3V eDP BOM Optional Signal Descr...

Page 38: ...DI1 A10 GBE0_MDI2 A6 GBE0_MDI2 A7 GBE0_MDI3 A2 GBE0_MDI3 A3 Gigabit Ethernet Controller 0 Media Dependent Interface Differential Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec modes Some pairs are unused in some modes per the following This set of differential pairs in conjunction with the GBE1_MDI 0 3 pairs may also be used to implement a 10 Gigabit sec interface I O Analog Twisted...

Page 39: ...orts SATA 3 0 SATA0_RX SATA0_RX A19 A20 Serial ATA channel 0 Receive Input differential pair I SATA Supports SATA 3 0 SATA1_TX SATA1_TX B16 B17 Serial ATA channel 1 Receive Input differential pair O SATA Supports SATA 3 0 SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA Supports SATA 3 0 SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Receive Input differential ...

Page 40: ...TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX3 PCIE_RX3 B58 B59 PCI Express channel 3 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX4 PCIE_TX4 A55 A56 PCI Express channel 4 Transmit Output differential pair O PCIE AC coupled on Module PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCI...

Page 41: ...Pin Description I O PU PD Comment USB0 USB0 A46 A45 USB differential data pairs for Port 0 I O 3 3VSB USB 1 1 2 0 compliant USB1 USB1 B46 B45 USB differential data pairs for Port 1 I O 3 3VSB USB 1 1 2 0 compliant USB2 USB2 A43 A42 USB differential data pairs for Port 1 I O 3 3VSB USB 1 1 2 0 compliant USB3 USB3 B43 B42 USB differential data pairs for Port 2 I O 3 3VSB USB 1 1 2 0 compliant USB4 U...

Page 42: ...y drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull high on carrier USB_6_7_OC A38 USB over current sense USB ports 6 and 7 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull high on carrier 4 4 11 SPI BIOS only Signal Pin Description I O PU PD Comment SPI_CS B97...

Page 43: ...ff module temp sensor indicating an over temp situation I 3 3V THERMTRIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3V FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fan s RPM O OD 3 3V PU 2 2K 3 3V PD shall be on the carrier board FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output I OD 3 3V P...

Page 44: ...put I O OD 3 3VSB PU 2k2 3 3VSB I2C_DAT B34 General purpose I C port data I O line I O OD 3 3VSB PU 2k2 3 3VSB 4 4 15 General Purpose I O GPIO Signal Pin Description I O PU PD Comment GPO 0 A93 General purpose output pins O 3 3V PU 10K 3 3V After hardware RESET output low GPO 1 B54 General purpose output pins O 3 3V PU 10K 3 3V After hardware RESET output low GPO 2 B57 General purpose output pins ...

Page 45: ...eiver TTL level input I CMOS I CMOS Power rail tolerance 5V 12V SER1_TX CAN_TX A101 General purpose serial port transmitter TTL level output O CMOS Power rail tolerance 5V 12V PD shall be on the carrier board SER1_RX CAN_RX A102 General purpose serial port receiver TTL level input I CMOS Power rail tolerance 5V 12V 4 4 17 Power and System Management Signal Pin Description I O PU PD Comment PWRBTN ...

Page 46: ...nent suspend operation used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used to enable the non standby power on a typical ATX power supply O 3 3VSB SUS_S4 A18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB SUS_S5 A24 Indicates system is in ...

Page 47: ...O PU PD Comment VCC_12V A104 A109 B104 B109 Primary power input 12V nominal 5 20V wide input All available VCC_12V pins on the connector s shall be used P 5 20 V VCC_5V_SBY B84 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in ...

Page 48: ...h on USB1 O PCIE AC coupled on Module USB_SSRX2 USB_SSRX2 C9 C10 Additional Receive signal differential pairs for the SuperSpeed USB data path on USB2 I PCIE USB_SSTX2 USB_SSTX2 D9 D10 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2 O PCIE AC coupled on Module USB_SSRX3 USB_SSRX3 C12 C13 Additional Receive signal differential pairs for the SuperSpeed USB data...

Page 49: ...37 C25 C26 C29 C30 C15 C16 Digital Display Interface1 differential pairs O PCIE Pair 4 to Pair 6 Not supported DDI1_HPD C24 Digital Display Interface Hot Plug Detect I PCIE PD 100K IF DDI1_DDC_AUX_SEL is floating I O PCIe DP1_AUX DDI1_CTRLCLK_AUX D15 IF DDI1_DDC_AUX_SEL pulled high I O OD 3 3V HDMI1_CTRLCLK IF DDI1_DDC_AUX_SEL is floating I O PCIe DP1_AUX DDI1_CTRLDATA_AUX D16 IF DDI1_DDC_AUX_SEL ...

Page 50: ...V HDMI2_CTRLCLK IF DDI2_DDC_AUX_SEL is floating I O PCIe DP2_AUX DDI2_CTRLDATA _AUX C33 IF DDI2_DDC_AUX_SEL pulled high I O OD 3 3V HDMI2_CTRLDATA DDI2_DDC_AUX _SEL C34 Selects the function of DDI2_CTRLCLK_AUX and DDI2_CTRLDATA_AUX This pin shall have a 1M pull down to logic ground on the Module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair conta...

Page 51: ...s used for the DP AUX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals PD 1M Not supported 4 5 4 DDI to DP HDMI SDVO Mapping Pin Pin Name DP HDMI DVI D26 DDI1_PAIR0 DP1_LANE0 TMDS1_DATA2 D27 DDI1_PAIR0 DP1_LANE0 TMDS1_DATA2 D29 DDI1_PAIR1 DP1_LANE1 TMDS1_DATA1 D30 DDI1_PAIR1 DP1_LANE1 TMDS1_DATA1 D32 DDI1_PAIR2 DP1_LANE2 TMDS1_DATA0 D33 DDI1_PAIR2 DP1_LANE2 TMDS1_DATA0...

Page 52: ...escription I O PU PD Comment The TYPE pins indicate to the Carrier Board the Pin out Type that is implemented on the Module The pins are tied on the Module to either ground GND or are no connects NC For Pin out Type 1 and Type 10 these pins are not present X TYPE0 C54 TYPE2 TYPE1 TYPE0 PDS X X X Pin out Type1 NC NC NC Pin out Type2 NC NC GND Pin out Type3 no IDE NC GND NC Pin out Type4 no PCI NC G...

Page 53: ...V wide input All available VCC_12V pins on the connector s shall be used P 5 20 V GND C1 C11 C21 C31 C41 C51 C60 C70 C76 C80 C84 C87 C90 C93 C96 C100 C103 C110 D1 D11 D21 D31 D41 D51 D60 D67 D70 D76 D80 D84 D87 D90 D93 D96 D100 D103 D110 Ground DC power and signal and AC signal return path All available GND connector pins shall be used and tied to carrierboard GND plane ...

Page 54: ...ory 5 2 I O Map Hex Range Device 000 01F N A 020 02D and 030 03F Interrupt controller 1 8259 equivalent 02E 02F LPC SIO configuration index data registers 040 043 Timer 8254 2 equivalent 04e 04f LPC SIO configuration index data registers 050 053 Timer 8254 2 equivalent 060 064 8742 equivalent keyboard 061 NMI control and status 070 077 Real Time Clock Controller bit 7 NMI mask 80 Port 80 debugger ...

Page 55: ...VGA registers 3E0 3E7 Available 3E8 3Ef Serial Port 3 3F0 3F7 Available 3F8 3FF Serial port 1 400 Alias for ICH TCO base address 4D0 4D1 Interrupt controller CF8 CFB PCI configuration address register 32 bit I O only CF9 Reset Control register 8 bit I O CFC CFF PCI configuration data register F040 Smbus base address for SB 1800 PM ACPI Base Address for SB 0A00 0AFF Reserved for SIO functions base ...

Page 56: ...PIRQ Note 1 13 FERR logic N A No 14 Generic IRQ14 via SERIRQ PIRQ Note 1 15 Generic IRQ15 via SERIRQ PIRQ Note 1 Note 1 These IRQs can be used for PCI devices when onboard device is disabled 5 3 2 APIC Mode IRQ Typical Interrupt Resource Connected to Pin Available 0 Counter 0 N A No 1 Keyboard controller IRQ1 via SERIRQ No 2 Cascade interrupt from slave PIC N A No 3 Serial Port 2 COM2 IRQ3 via SER...

Page 57: ...PCI devices when onboard device is disabled 5 4 PCI Configuration Space Map Bus Number Device Number Function Number Routing Description 00h 00h 00h N A Intel host Bridge 00h 01h 00h Internal Intel PCI Express Graphics port 00h 02h 00h Internal Intel I G D 00h 08h 00h Internal Gaussian Mixture Model 00h 14h 00h Internal xHCI Controller 00h 16h 00h Internal Intel Management Engine Interface 00h 17h...

Page 58: ...ler Int0 N A INTA 16 INTA 16 INTA 16 INTA 16 Int1 N A INTD 19 Int2 N A INTC 18 Int3 N A INTD 19 INTB 17 INT Line PCIE Port1 PCIE Port9 PCIE Port10 PCIE Port11 PCIE Port12 Int0 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 Int1 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 Int2 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 Int3 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 INT Line LPC Controller SATA Controller SMBus Con...

Page 59: ... Information Memory Information System Date and Time Advanced Trusted Computing CPU Configuration ACPI Settings AMT Configuration PCH FW Configuration SMART Settings W83627DHG Super IO Configuration NCT5104DSEC Super IO Configuration NCT7802Y HW Monitor CSM Configuration NVMe Configuration USB Configuration SATA Configuration Trusted Computing Chipset System Agent SA Configuration PCH IO Configura...

Page 60: ...ate and Time Feature Options Description System Date Week day MM DD YYYY Requires the alpha numeric entry of the day of the week day of the month calendar month and all 4 digits of the year indicating the century and year Fri XX XX 20XX System Time HH MM SS Presented as a 24 hour clock setting in hours minutes and seconds 6 2 Advanced 6 2 1 Trusted Computing Feature Options Description Security De...

Page 61: ...x CPU speed Info only Display Max CPU speed Min CPU speed Info only Display Min CPU speed CPU Speed Info only Display CPU Speed Processor Cores Info only Display Processor Cores Hyper Threading Technology Info only Display Intel HT Technology support or not Intel VT x Technology Info only Display Intel VT x Technology support or not Intel SMX Technology Info only Display Intel SMX Technology suppo...

Page 62: ...e the Mid Level Cache L2 streamer prefetcher Adjacent Cache Line Prefetch Disabled Enabled Enable the Mid Level Cache L2 prefetching of adjacent cache lines CPU AES Disabled Enabled Enable Disable CPU Advanced Encryption Standard instructions Boot performance mode Max Battery Max Non Turbo Performance Turbo Performance Select the performance state that the BIOS will set before OS handoff Intel R S...

Page 63: ...ditional firmware in the SPI device BIOS Hotkey Pressed Disabled Enabled Enable Disable BIOS hotkey press MEBx Selection Screen Disabled Enabled Enable Disable MEBx selection screen Hide Un Configure ME Confirmation Prompt Disabled Enabled Hide Un Configure ME without password Confirmation Prompt MEBx Debug Message Output Disabled Enabled Enable MEBx debug message output Un Configure ME Disabled E...

Page 64: ...tion Feature Options Description W83627DHG Super IO Configuration Info only Super IO Chip Info only Feature Options Description Serial Port Enabled Disabled Enable or Disable Serial Port COM Device Settings IO 3F8h IRQ 4 Fixed configuration of serial port Serial Port 1 Configuration Serial Port Submenu Change Settings Auto IO 3F8h IRQ 4 IO 3F8h IRQ 3 4 5 6 7 9 10 11 12 IO 2F8h IRQ 3 4 5 6 7 9 10 1...

Page 65: ...s Info only Smart Fan Function Disabled Enabled Enable or Disable Smart Fan Feature Options Description CPU Fan Control Smart Duty Cycle Mode Manual Duty Mode Smart Fan Mode Select Temperature 1 35 Specifies the temperature threshold at which the H W monitor turns on CPU fan with specific PWM duty cycle 1 Temperature 2 45 Specifies the temperature threshold at which the H W monitor turns on CPU fa...

Page 66: ...f the V1 2 1 05V Read only Display actual voltage of the V1 05 6 2 8 NVMe Configuration 6 2 9 USB Configuration Feature Options Description USB Configuration Info only USB Module Version Info only USB Controllers Info only X XHCI USB Devices Info only X Drive X Keyboards X Mouse X Hubs Legacy USB Support Enabled Disabled Auto Enables legacy USB support Auto option disables legacy support if no USB...

Page 67: ...st Controller Auto uses default value for a Root port it is 100 ms for a Hub port the delay is taken from Hub descriptor Mass Storage Devices Info only List current USB max stroge device 6 2 10 SATA Configuration Feature Options Description SATA Controller s Enabled Disabled Enable or disable SATA Device SATA Mode Selection AHCI RAID Determines how SATA controller s operate Feature Options Descrip...

Page 68: ...d Enabled Enable or Disable SATA Port 6 2 11 System Agent SA Configuration Feature Options Description System Agent Bridge Name Info only Display System Agent Bridge name SA PCIe Code Version Info only VT d Info only Check VT d function on System Agent VT d Disabled Enabled VT d capability Feature Options Description Graphics Configuration Info only IGFX VBIOS Version Info only Display VBIOS Versi...

Page 69: ...T 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics Device DVMT Total Gfx Mem XXXM Select DVMT5 0 Total Graphic Memory size used by the Internal Graphics Device Feature Options Description LCD Control Info only LCD Panel Type VBIOS Default 640X480 LVDS 800X600 LVDS 1024X768 LVDS 1280X1024 LVDS 1400X1050 LVDS1 1400X1050 LVDS2 1600X1200 LVDS 1366X768 LVDS 1680X1050 LVDS 1920...

Page 70: ... Configuration Info only PEG 0 1 0 Not Present Display PEG0 present or not Enable Root Port Disabled Enabled Auto Enable or Disable the Root Port Max Link Speed Auto Gen1 Gen2 Gen3 Configure PEG 0 1 0 Max Speed PEG 0 1 1 Not Present Display PEG1 present or not Enable Root Port Disabled Enabled Auto Enable or Disable the Root Port Max Link Speed Auto Gen1 Gen2 Gen3 Configure PEG 0 1 1 Max Speed PEG...

Page 71: ... Intel PCH Rev ID Info only Display Intel PCH Revision ID Feature Options Description PCI Express Configuration Info only PCI Express Clock gating Disable Enable Enable or disable PCI Express Clock Gating for each root port DMI Link ASPM Control Disable Enable Enable Disable the control of Active State Power Management on SA side of the DMI link PCI Express Root Port X Disabled Enabled Control the...

Page 72: ... port speed Feature Options Description USB Configuration Info only USB Precondition Enabled Disabled Precondition work on USB host controller and root ports for faster enumeration XHCI Disable Compliance Mode FALSE TRUE Options to disable Compliance Mode Default is FALSE to not disable Compliance Mode Set TRUE to disable Compliance Mode USB Configuration Submenu USB Port Disable Override Disabled...

Page 73: ...mpt Timeout 1 Number of seconds to wait for setup activation key 65535 0xFFFF means indefinite waiting Bootup NumLock State On Off Select the keyboard NumLock state Quiet Boot Disabled Enabled Enables or disables Quiet Boot option Boot Option filter UEFI and Legacy Legacy only UEFI only This option controls Legacy YEFI ROMs priority Boot Option Priorities Info only Boot Option X Selection Sets the...

Page 74: ...em after saving the changes Discard Changes and Reset Reset system setup without saving any changes Default Options Feature Options Description Restore Defaults Restore Load Default values for all the setup options Boot Override Feature Options Description Boot Override Info only ...

Page 75: ...ery errors PEI 7 2 Standard Status Codes 7 2 1 SEC Status Codes Status Code Range Description Not used Progress Codes 0x1 Power on Reset type detection soft hard 0x2 AP initialization before microcode loading 0x3 North Bridge initialization before microcode loading 0x4 South Bridge initialization before microcode loading 0x5 OEM initialization before microcode loading 0x6 Microcode loading 0x7 AP ...

Page 76: ...ule specific 0x18 Pre Memory North Bridge initialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory South Bridge initialization South Bridge module specific 0x1C Pre memory South Bridge initialization South Bridge module specific 0x1D 0x2A OEM pre memory initialization ...

Page 77: ... Memory South Bridge initialization South Bridge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory initialization error SPD reading has failed 0x52 Memory initialization error Invalid memory size or memory modules do not match 0x53 Memory initialization...

Page 78: ...ser Forced recovery 0xF2 Recovery process started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB 0xFF Reserved for future AMI error codes 7 2 4 PEI Beep Codes Number of Beeps Description 1 Memory...

Page 79: ...nitialization North Bridge module specific 0x70 South Bridge DXE initialization is started 0x71 South Bridge DXE SMM initialization is started 0x72 South Bridge devices initialization 0x73 South Bridge DXE Initialization South Bridge module specific 0x74 South Bridge DXE Initialization South Bridge module specific 0x75 South Bridge DXE Initialization South Bridge module specific 0x76 South Bridge ...

Page 80: ...L Status Codes section below 0xAB Setup Input Wait 0xAC Reserved for ASL see ASL Status Codes section below 0xAD Ready To Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean up of NVRAM 0xB7 Config...

Page 81: ...No Console Input or Output Devices are found 1 Invalid password 6 Flash update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met 7 2 7 ACPI ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 System is entering S2 sleep state 0x03 System is entering S3 sleep state 0x04 System is entering S4 sleep state 0x05 System is enter...

Page 82: ...on after microcode loading 0x1D 0x2A OEM pre memory initialization codes 0x3F 0x4E OEM PEI post memory initialization codes 0x80 0x8F OEM DXE initialization codes 0xC0 0xCF OEM BDS initialization codes Contact Information North Andover Mass Headquarters WIN Enterprises Inc 300 Willow Street North Andover Mass 01845 1 978 688 2000 sales win ent com 1 978 688 4884 www win ent com ...

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Summary of Contents for MB-73440

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Summary of Contents for MB-73440

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