WIENER, Plein & Baus GmbH
7
www.wiener-d.com
1.6 Block diagram
I1
- User NIM input
O1
- User NIM "Busy" output
ACQ
- Data Acquisition Control
REG
-
Register
Block
STACKS
- CAMAC Command Stacks (2 kBytes)
NAF
- NAF Sequence Generator
CAMAC
- CAMAC Bus, Including Arbitration
FIFOs
- Three-Stage Piplined FIFO Array (22 kBytes)
Master
- Control Unit
USB Controller
- FX2 CY7C68013 IC
OUT FIFO
- USB Out FIFO (Relative to Host)
IN FIFO
- USB In FIFO (Relative to Host)
CAMAC
FIFOs
OUT
F
IFO
IN
FIFO
NAF
USB
C
ONT
R
OLLE
R
REG
STACKS
ACQ
I1
MAST
ER
External to
FPGA
Data
Control
O1
