Western Digital Purple PR1000M, Technical Reference Manual

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ATA C
OMMAND
S
ET PR1000M
32 RELEASED 5/8/17 (WD CONFIDENTIAL) 2679-800020-A03
50 Capabilities
Bit 15: Shall be cleared to zero.
Bit 14: Shall be set to one.
Bit 13-2: Reserved.
Bit 1: Obsolete
Bit 0: Shall be set to one to indicate a device specific
Standby timer value minimum
4001
H
51-52 Obsolete
0
53 Additional Words Valid
Bit 8-15: Free-fall Control Sensitivity
00h = Vendor’s recommended setting
01h-FFh = Sensitivity level. A larger number is a
more sensitive setting.
Bit 7-3: Reserved
Bit 2: If set, the fields reported in word 88 are valid
Bit 1: If set, the fields reported in words 70-64 are valid
Bit 0: Obsolete
0007
H
54-58 Obsolete
0
59 Current Blocking Factor
Bit 15: 1=The BLOCK ERASE EXT command is supported
Bit 14: 1= The OVERWRITE EXT command is supported
Bit 13: 1=The CRYPTO Scramble EXT command is
supported
Bit 12: 1=The Sanitize feature set is supported
Bit 9-11 Reserved
Bit 8: 1=Multiple local sector setting is valid
Bit 0-7: Current setting for number of logical sectors that
shall be transferred per DRQ data block on READ/WRITE
Multiple commands
XX
H
60-61 Total number of user addressable logical sectors for 28
bit commands (DWord)
0FFFFFFF
H
62 Obsolete
0
63 Multi-Word DMA Transfer Mode Supported
Bit 15-11: Reserved
Bit 10: If set, Multiword DMA mode 2 is selected
Bit 9: If set, Multiword DMA mode 1 is selected
Bit 8: If set, Multiword DMA mode 0 is selected
Bit 7-3: Reserved
Bit 2: If set, Multiword DMA mode 2
Bit 1: If set, Multiword DMA mode 1
Bit 0: If set, Multiword DMA mode 0
XX07
H
64 Advanced PIO Modes Supported
Bits 0-7: PIO Modes supported
0003
H
65 Min. Multi-Word DMA Transfer Cycle Time (ns)
Bit 15-0: Cycle time in nanoseconds
120
66 Manufacturer Recommended Multi-Word DMA Cycle Time
Bit 15-0: Cycle time in nanoseconds
120
67 Min. PIO Transfer Cycle Time without flow control
Bit 15-0: Cycle time in nanoseconds
120
68 Min. PIO Transfer Cycle Time with IORDY flow control
Bit 15-0: Cycle time in nanoseconds
120