Watec WAT-910BD, Communications Manual

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WAT-910BD SPI COMMUNICATION MANUAL(Digital Out)
5.2.1 CLOCK PHASE (CLK PHASE)
By using the bit-3, the phase of digital output clock signal DCK (connector: J6, pin number: 4) is inverted.
Camera Parameter
*Factory setting value: 0x47
*1) CLK PHASE=0(factory setting):
In synchronization with the rising edge of the DCK, the digital video data is output.
DCK
*2)CLK PHASE=1:
In synchronization with the falling edge of the DCK, the digital video data is output.
DCK
e.g.3) To be synchronized with the falling edge of the data output by changing the DCK phase.
(digital output ON, others are left at the default setting)
The data byte to be transmitted to the digital output setting(address: 0x193) is 0xCF.
Send following data bytes to the indirect registers for SPI control (address: 0x0036 to 0x003B).
1 1
1:ON 1: 1-254 2:Cr,Y,Cb,Y 3:Y,Cr,Y,Cb 1:↓
Address
Bit
7 6 5 4 3 2 1 0
5.2 DETAIL SETTINGS
Bit 7 6 5 4 3 2 1 0
0x193
DIGIT OUT DYC RANGE COLOR ID CLK PHASE (fixed) (fixed) (fixed)
0:OFF 0:16-235 0:Cb,Y,Cr,Y 1:Y,Cb,Y,Cr 0:↑
1
Yn+4
Parameter
DIGIT OUT DYC RANGE COLOR ID CLK PHASE
D7-D0 OUT Yn 80 Yn+1 80 Yn+2 80 Yn+3 80
1:ON 1:1-254 0:Cb,Y,Cr,Y 1:↓
(fixed) (fixed) (fixed)
D7-D0 OUT Yn 80 Yn+1 80 Yn+2 80 Yn+3 80 Yn+4
bit setting 1 1 0 0 1 1 1 1
data value 0xCF
address 0x36 0x37 0x38 0x39 0x3A 0x3B
symbol C1 C2 ADR DAT CS ST
value(hex) 04 82 93 CF E8 AA
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