VXIS VX1828B, Datasheet, Page: 44 / 64

VX1828B
Preliminary Datasheet Video Processor for Middle Size LCD Panel
P.44/P.64
V1.0 050420
6.2.10 OUTPUT FORMAT REGISTERS
Bit Map Addr.
(Hex)
Name
Def.
(Hex)
7 6 5 4 3 2 1 0
3A OS7 00
AOUT_
OFF
VOCLKP HSYNCP VSYNCP VOCLKD2 -
OTRI_
CLK
OTRI
3B OS8 A9 HS_WIDTH VS_WIDTH
3C OS9 94 HSHIFT
3D OSA 00 VSHIFT
3E OSB 00 BOTTOM_MASK
3F OSC 00 TOP_MASK
40 OSD 00 LEFT_MASK
41 OSE 00 RIGHT_MASK
42 OSF 00 PG_SEL PG_LEVEL
AOUT_OFF Analog video output disable
VOCLKP Change the polarity of AVCLK (TCON clock)
HSYNCP Pin HSYNC polarity
VSYNCP Pin VSYNC polarity
VOCLKD2 0 VOCLK’s frequency equals 1x output data rate (df.)
1 VOCLK’s frequency equals 0.5x output data rate
OTRI_CLK VOCLK high impedance enable
OTRI Video/Hsync/Vsync outputs high impedance enable
HS_WIDTH Width of video output horizontal synchronization
Actual synchronization-width = 13 + (HS_WIDTH x 4) in pixels
VS_WIDTH Width of video output vertical synchronization
Actual synchronization-width = 1 + VS_WIDTH in lines
HSHIFT Video output horizontal shifting
VSHIFT Video output vertical shifting
BOTTOM_MASK Number of lines masked from the bottom of a frame
TOP_MASK Number of lines masked from the top of a frame
LEFT_MASK Number of pixels masked from the left-hand-side of a frame
RIGHT_MASK Number of pixels masked from the right-hand-side of a frame
PG_SEL Embedded pattern type selection
PG_LEVEL Gray level of embedded pattern (= ho to h1F, 32 steps)
Table 6.2.10.1 Embedded pattern selection
PG_SEL Pattern Type Gray level
000 None -
001 Red field 32
010 Green field 32
011 Blue field 32
100 White field 32
101 Black field 32
110 DAC Min. Output -
111 DAC Max. Output -