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SVM2608 Programming

31

With a variety of systems and bridges that move the data between different bus types (i.e. VME to
PCI, VXI to PCI, etc.), in order to assist the user in determining how data is ordered, a known
floating point value of 0.12345678901234 is loaded at Power-Up in the Result Register for all
channels. Channel 0 values are listed as an illustration:

0x3FBF

is written at address

0xC00028

0x9ADD

is written at address

0xC0002A

0x3746

is written at address

0xC0002C

0xF4C6

is written at address

0xC0002E

By reading the value from these addresses, the user can identify the type of DATA(BYTE)
swapping that takes place in the system and modify their code accordingly. An example of how to
do the swapping is presented in Appendix A.

D

ETERMINING THE

R

EGISTER

A

DDRESS

A user wishes to set Channel 2 to the 1.0 V range. Data is to be captured linearly without the use
of the low pass filter or timeout control and will trigger from the positive edge of data sent to
Channel 2. To accomplish this, the user will access the Control Register for Channel 2 at register
offset 0x0058. To determine the register address, this value must be added to the base address and
A32 address of the module. In this example, it is assumed that the base address switches are set to
0x19, yielding a base address of 0x19000000. Since the user must write to a register, the function
offset is 0x00C00000.

Register Address = Module Base A Function Register Offset

= 0x19 0x00 0x00000058

=

0x19C00058

By observing the bits in the Control Register, it can be determined what data value should be sent:

0x

58

(C

ha

nn

el

2 O

ffs

et

)

It is recommended that unused register bits
have 0 written to them

Disables Timeout Control

Sets the Channel for Linear Acquisition

Sets the Channel for Voltage Mode

Sets the Channel for acquisition in the 1.0 V range

Disables the 20 kHz Filter on Channel 2

Sets the channel to trigger on a Positive Slope

Selects Channel 2 as the Trigger Source

Write

Reason

D6

D5

D4

D3

D2

D1

D0

D15

D14

D13

D12

D10

D11

D9

D8

D7

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

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30
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»

Summary of Contents for SVM2608

Page 1: ...SVM2608 4 Channel 100 kSamples s Analog to Digital Converter USER S MANUAL P N 82 0066 000 Released February 23 2007 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 949 955 1894 ...

Page 2: ...VXI Technology Inc 2 ...

Page 3: ...Mode 15 Calibrations 15 Test Bus 15 Commands 15 Option 01 16 Physical Description 18 Front Panel Interface Wiring 19 SVM2608 Specifications 20 SECTION 2 23 PREPARATION FOR USE 23 Introduction 23 Calculating System Power and Cooling Requirements 23 Setting the Chassis Backplane Jumpers 23 Setting the Base Address 24 Example 1 25 Example 2 26 Module Installation Removal 26 SECTION 3 27 PROGRAMMING 2...

Page 4: ...Error Processing 47 Diagnostic Commands 49 Examples 51 Example 1 Setting the Channel 2 and 4 Sample Rate to 123 ms 8 13 kHz 51 Example 2 Setting Channel 2 to Acquire 200 000 Samples 51 Example 3 Setting Channel 2 to Pre acquire 100 000 Samples 52 Example 4 Setting Channel 2 to Delay Acquisition by 1 500 000 Samples 52 Example 5 Setting Channel 2 and 4 Timeout Register to Timeout after 2 5 s 53 APP...

Page 5: ... duties and taxes for products returned to VTI from another country VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming when properly installed on that product VTI does not however warrant that the operation of the product or software or firmware will be uninterrupted or error free LIMITATION OF WARRANTY The warranty shall not apply to ...

Page 6: ...Directive 89 366 EEC inclusive 93 68 EEC and carries the CE mark accordingly The product has been designed and manufactured according to the following specifications SAFETY EN61010 2001 EMC EN61326 1997 w A1 98 Class A CISPR 22 1997 Class A VCCI April 2000 Class A ICES 003 Class A ANSI C63 4 1992 AS NZS 3548 w A1 A2 97 Class A FCC Part 15 Subpart B Class A EN 61010 1 2001 The product was installed...

Page 7: ...r loss of data These symbols may appear on the product ATTENTION Important safety instructions Frame or chassis ground Indicates that the product was manufactured after August 13 2005 This mark is placed in accordance with EN 50419 Marking of electrical and electronic equipment in accordance with Article 11 2 of Directive 2002 96 EC WEEE End of life product can be returned to VTI by obtaining an R...

Page 8: ...void electric shock the grounding conductor must be connected to earth ground Operating Conditions To avoid injury electric shock or fire hazard Do not operate in wet or damp conditions Do not operate in an explosive atmosphere Operate or store only in specified temperature range Provide proper clearance for product ventilation to prevent overheating DO NOT operate if any damage to this product is...

Page 9: ...949 955 1894 Fax 949 955 3041 VXI Technology Cleveland Instrument Division 5425 Warner Road Suite 13 Valley View OH 44125 Phone 216 447 8950 Fax 216 447 8951 VXI Technology Lake Stevens Instrument Division VXI Technology Inc 1924 203 Bickford Snohomish WA 98290 Phone 425 212 2285 Fax 425 212 2289 Technical Support Phone 949 955 1894 Fax 949 955 3041 E mail support vxitech com Visit http www vxitec...

Page 10: ...VXI Technology Inc 10 SVM2608 Preface ...

Page 11: ... 01 Option can include two high speed 20 MHz channels OVERVIEW The SVM2608 is a precision four channel digitizer capable of capturing data on all four channels simultaneously either in FIFO or real time mode or Linear or burst mode A processor enables the user to perform a variety of calculations with the data acquired Each channel is also capable of measuring voltage and resistance All four chann...

Page 12: ...vailable to the microprocessor for data processing The samples are stored as words 16 bits The first sample of a channel is located at the channel s base address at Offset 0 0x000000 for Channel 0 0x200000 for Channel 1 0x400000 for Channel 2 and 0x600000 for Channel 3 The next sample is located at Offset 2 0x000002 for Channel 0 etc and the third sample is located at Offset 4 etc In order to prov...

Page 13: ...ata will be lost It is also NOT possible to run a measurement command in FIFO mode Acquiring Data To acquire data a channel must first be Armed When a channel is armed it starts its local Sample Clock and waits for a Trigger Event to begin sampling The channel must remain Armed for the entire duration of the acquisition process Clearing the ARM bit will reset the internal state machines and stop a...

Page 14: ... following equation AFTER TRIGGER POINTS SAMPLE POINTS PRETRIGGER POINTS When the user reads from offset zero of a channel the data returned is Sample Zero followed by Sample Zero 1 etc The Pre Trigger Points can be read from the top of that channel s memory For example if 0x100 Pre Trigger Points were sampled on Channel 0 after the acquisition is completed the samples can be retrieved from locati...

Page 15: ... dramatically increase the cost of the board Another way to compensate for offset and gain variations is to take a number of measurements using precision calibrated instruments of known voltage and resistance Their known values are then compared against the values attained for each channel and the difference is used to adjust future measurements These adjustments are called calibrations They are p...

Page 16: ...alues the exact values injected in the resistance under test by the board s current source Although it is possible for the user to read the calibration values see the Calibration Commands section and use the raw data to perform all the calibrated measurements on their own the manufacturer encourages the use of the microprocessor s capabilities to perform all calibrated resistance calculations Opti...

Page 17: ...L SINGLE HIGH SPEED CHANNEL DAC REF_LVL ADC SINGLE DIFF TO GLUE LOGIC CHANNEL_1 TRIG CHANNEL_5 TRIG EXT_TRG TRIG REFERENCE ADJ CHNL TRIG HS_EXT_TRIG DAC EXT_TRIG_LVL CHNL TRIG DATA CONTROLS 16 BITS 10 MHz VM2608 MAIN BOARD 16 BITS 120 MHz SDRAM 2 MB TRIG_LVL OFFSET_LVL HS_TRIG_LVL LS_TRIG HS_TRIG REF_LVL LOW_SPEED_CHNLS FIGURE 1 2 SVM2608 BLOCK DIAGRAM ...

Page 18: ...ndensing ALTITUDE OPERATIONAL SUSTAINED STORAGE Sea level to 15 000 ft 4 570 m Sea level to 40 000 ft 12 190 m RANDOM VIBRATION OPERATIONAL NON OPERATIONAL Three axis 30 minutes total 10 minutes per axis 0 27 grms total from 5 0 Hz to 55 0 Hz 2 28 grms total from 5 0 Hz to 55 0 Hz FUNCTIONAL SHOCK Half sine 30 g 11 ms duration SALT ATMOSPHERE 48 hrs operation SAND AND DUST 6 hrs operation in a dus...

Page 19: ... with the high speed channels are labeled on the front panel and are capable of being triggered by a different external trigger source than the low speed channels PIN NUMBER SIGNAL PIN NUMBER SIGNAL PIN NUMBER SIGNAL 1 GND 13 TB 25 GND 2 CH1I 14 GND 26 CH3I 3 CH1 15 GND 27 CH3 4 CH1 16 GND 28 CH3 5 CH1I 17 GND 29 CH3I 6 GND 18 GND 30 GND 7 GND 19 EXTTRIGIN 31 GND 8 CH0I 20 GND 32 CH2I 9 CH0 21 GND...

Page 20: ...MENT Range Resolution Accuracy 100 Ω 1 kΩ 10 kΩ 100 kΩ 1 MΩ 100 over range 1 6 553 6 of scale 1 Note Resistance measurements can only be made one channel at a time All resistance measurements can be made accurately up to 199 of the set range INPUT FILTER 20 kHz 3 dB TRIGGER LEVELS Internal Range Trigger level resolution Level accuracy External Range Trigger level resolution Level accuracy trigger ...

Page 21: ...re selectable INPUT MODE ac or dc software selectable INPUT FILTER 5 MHz 3 dB TRIGGER LEVELS Internal Range Trigger level resolution Level accuracy External Range Trigger level resolution Level accuracy trigger level determined by selected voltage range see Voltage Measurement above Full scale 211 1 10 V to 10 V 4 88 mV 1 DELAYED TRIGGER Range Resolution 0 samples to 224 1 samples 1 sample TRIGGER...

Page 22: ...VXI Technology Inc 22 SVM2608 Introduction ...

Page 23: ...red After setting the base address and chassis jumpers the SVM2608 may be installed into an appropriate 6U VMEbus mainframe in any slot other than slot zero CALCULATING SYSTEM POWER AND COOLING REQUIREMENTS It is imperative that the chassis provide adequate power and cooling for this module Referring to the chassis operation manual confirm that the power budget for the system the chassis and all m...

Page 24: ... address space The switches are labeled with positions 0 through F The switch located at S3 corresponds to the Most Significant Bit MSB and S2 corresponds to the Least Significant Bit LSB Note S1 is not used in the determination of the base address To set the OV to 25 first convert the decimal number to the hexadecimal value of 0x19 Next set switch S3 to 1 and then set switch S2 to 9 See Figure 2 ...

Page 25: ...imal Set the back switch to 1 and the front switch to 9 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F S2 S3 FIGURE 2 2 OFFSET VALUE EXAMPLE 1 Here is another way of looking at the conversion OV S3 x 16 S2 OV 1 x 16 9 OV 16 9 OV 25 The base address is then determined by using the following formula A32 Base Address Offset Value 0x1000000 or 16 777 216 In this case A32 Base Address ...

Page 26: ...ls on SVM2608 registers MODULE INSTALLATION REMOVAL Before installing an SVM2608 module into a 6U VME mainframe make sure that the mainframe is powered down Insert the module into the base unit by orienting the module so that the flanges at the edge of the module can be inserted into the slot of the base unit Position the flanges so that they fit into the module slot groove Once the module is prop...

Page 27: ...4 0x400000 CH3 Data 6291456 0x600000 CH4 Option 01 8388608 0x800000 CH5 Option 01 10485760 0xA00000 Registers 12582912 0xC00000 Reserved 14680064 0xE00000 CH0 5 Data These addresses are used to store data Registers These addresses are the A32 memory registers They are used to program the settings for each channel collect FIFO data collect results or sent commands to the microprocessor Reserved The...

Page 28: ...mand Register Channel 0 Command Register Channel 0 0x24 Reserved FIFO Data Channel 0 MS 0x26 Reserved FIFO Data Channel 0 LS 0x28 Reserved Result Register Channel 0 MS 0x2A Reserved Result Register Channel 0 LS 0x2C Reserved Result Register Channel 0 MS 0x2E Reserved Result Register Channel 0 LS 0x30 Control Channel 1 Control Channel 1 0x32 Trigger Level Channel 1 Trigger Level Channel 1 0x34 Samp...

Page 29: ...nel 3 0x82 Trigger Level Channel 3 Trigger Level Channel 3 0x84 Sample Rate Channel 3 MS Sample Rate Channel 3 MS 0x86 Sample Rate Channel 3 LS Sample Rate Channel 3 LS 0x88 Sample Points Channel 3 MS Sample Points Channel 3 MS 0x8A Sample Points Channel 3 LS Sample Points Channel 3 LS 0x8C Pre Trigger Points Channel 3 MS Pre Trigger Points Channel 3 MS 0x8E Pre Trigger Points Channel 3 LS Pre Tri...

Page 30: ...gger Points Channel 5 LS Pre Trigger Points Channel 5 LS 0xE0 Trigger Delay Channel 5 MS Trigger Delay Channel 5 MS 0xE2 Trigger Delay Channel 5 LS Trigger Delay Channel 5 LS 0xE4 Timeout Channel 5 Timeout Channel 5 0xE6 Interrupt Enable Channel 5 Interrupt Enable Channel 5 0xE8 Reserved Interrupt Status Channel 5 0xEA Command Register Channel 5 Command Register Channel 5 0xEC Reserved FIFO Data C...

Page 31: ... trigger from the positive edge of data sent to Channel 2 To accomplish this the user will access the Control Register for Channel 2 at register offset 0x0058 To determine the register address this value must be added to the base address and A32 address of the module In this example it is assumed that the base address switches are set to 0x19 yielding a base address of 0x19000000 Since the user mu...

Page 32: ... bits from a 16 bit register may generate a BERR on the VME bus Writing 32 bits to a 16 bit register may generate a BERR on the VME bus or may corrupt data in another register DESCRIPTION OF REGISTERS The following pages describe the registers found in the SVM2608 Register Map for A32 address space that starts at 0x00C0000 When multiple channels registers have the same functions the offsets appear...

Page 33: ...only utilized by high speed Channels 4 and 5 These bits are unused for Channels 0 3 D12 EXT TRIG SLOPE External Trigger Slope This bit sets the slope of the external trigger for low speed Channels 0 3 0 Positive 1 Negative Note This bit is only utilized by high speed Channels 4 and 5 This bit is unused for Channels 0 3 D11 D6 FTRIG5 0 Force Trigger All of the channels have the ability to be trigge...

Page 34: ...rigger Level 0x06 Read Write D15 D12 Unused These bits are reserved for future use D11 D0 External Trigger Level Sets the level at which the module triggers from an external source Control Register 0x08 0x30 0x58 0x80 0xA8 0xD0 Read Write D15 D14 Unused These bits are reserved for future use D13 AC DC Coupling AC DC Select This bit selects between ac and dc coupling for high speed Channels 4 5 0 A...

Page 35: ...hannels 4 and 5 D7 D5 ATTN GAIN1 GAIN0 Attenuation and Gain Setting Valid attenuation settings are x1 and x10 Valid gain settings are 1 2 5 and 10 Note that there is only one current source shared among all four channels therefore only one resistance measurement can be made at any one time Before taking a measurement allow for at least 5 ms for internal circuits to settle after making changes VOLT...

Page 36: ...tion can be triggered via software FTRIG any of the six channels or an external trigger 000 Channel 0 001 Channel 1 010 Channel 2 011 Channel 3 100 Channel 4 101 Channel 5 110 External 111 External High Speed Sample Rate 0x0C 0x34 0x5C 0x84 Read Write D15 D9 Unused These bits are reserved for future use D8 D0 SAMPRAT24 16 Sample Interval These bits set the sample rate Bit Weight 100 ns bit Minimum...

Page 37: ... SIZE15 0 Waveform Capture Size In Linear mode this sets the number of data points to be captured in a single sweep In FIFO mode this sets the threshold for generating a service request interrupt or status bit The maximum size is 1 MSamples 2 Mbytes of data Pre Trigger Points 0x14 0x3C 0x64 0x8C 0xB4 0xDC Read Write D15 D4 Unused These bits are reserved for future use D3 D0 PRE19 16 Size of Pre Tr...

Page 38: ... actual timeout setting Interrupt Enable 0x1E 0x46 0x6E 0x96 0xBE 0xE6 Read Write D15 D0 IM15 0 Interrupt Enable Enables or disables interrupt generation for corresponding bit in the interrupt status register 0 Disabled 1 Enabled Pon state 0 Interrupt Status 0x20 0x48 0x70 0x98 0xC0 0xE8 Read Only D15 D0 INT15 0 Interrupt Status Register If a corresponding bit in the interrupt enable register is s...

Page 39: ...ter 0x2A 0x52 0x7A 0xA2 0xCA 0xF2 Read Only D15 D0 RESULT47 32 Result Data When a process data command is issued to the microprocessor bits 47 through 32 of the 64 bit floating point result is returned to this register A status bit in the interrupt register is set Results Register 0x2C 0x54 0x7C 0xA4 0xCB 0xF4 Read Only D15 D0 RESULT31 16 Result Data When a process data command is issued to the mi...

Page 40: ...OST TRIGGER DATA m Sample Size n 1 TRIGGER DELAY DATA n of Pre Trigger Points PRE TRIGGER DATA POST DELAY DATA PRE TRIGGER DATA n of Pre Trigger Points Trigger Sample 2 Post Delay Data 2 Trigger Sample m Post Delay Data m Trigger Sample n Trigger Sample Trigger Sample 2 Trigger Sample 1 Trigger Sample 1 Trigger Sample n 0x00000 0x00002 0x00004 0xFFFFC 0xFFFFE FIGURE 3 1 MEMORY MAP ...

Page 41: ...urement 2 wire 0x0006 1 kΩ Range Resistance Measurement 2 wire 0x0007 10 kΩ Range Resistance Measurement 2 wire 0x0008 100 kΩ Range Resistance Measurement 2 wire 0x0009 1 MΩ Range Resistance Measurement 2 wire 0x000A Auto range Resistance Measurement 2 wire 0x000B 100 Ω Range Resistance Measurement 4 wire 0x000C 1 kΩ Range Resistance Measurement 4 wire 0x000D 10 kΩ Range Resistance Measurement 4 w...

Page 42: ...urement Dynamic Method 2 wire 0x0033 Auto Range Resistance Measurement Dynamic Method 2 wire 0x0034 100 Ω Range Resistance Measurement Dynamic Method 4 wire 0x0035 1 kΩ Range Resistance Measurement Dynamic Method 4 wire 0x0036 10 kΩ Range Resistance Measurement Dynamic Method 4 wire 0x0037 100 kΩ Range Resistance Measurement Dynamic Method 4 wire 0x0038 1 MΩ Range Resistance Measurement Dynamic Me...

Page 43: ... In this instance current is turned off for the second measurement I2 0 In effect this measurement is the same as an offset resistance measurement Self Test Command The Perform Self Test 0x0011 command instructs the processor to perform an internal test using the on board reference voltage and on board reference resistors The purpose of this test is to verify the functionality and accuracy of the ...

Page 44: ...r a Self Test command indicated a problem during Self Test 0 and Self Test 1 measuring 0 945 V on the 2 V scale but no problem on all other tests This would indicate that the front end programmable gain amplifier has a problem on the x5 gain 5 setting Example 2 Reading 0x00000000 after a Self Test operation would indicate that all Self Tests passed successfully Preset Setting Measurement Commands ...

Page 45: ...x0030 10 kΩ Range Resistance Measurement Dynamic Method 2 wire 0x0031 100 kΩ Range Resistance Measurement Dynamic Method 2 wire 0x0032 1 MΩ Range Resistance Measurement Dynamic Method 2 wire 0x0033 Auto Range Resistance Measurement Dynamic Method 2 wire 0x0034 100 Ω Range Resistance Measurement Dynamic Method 4 wire 0x0035 1 kΩ Range Resistance Measurement Dynamic Method 4 wire 0x0036 10 kΩ Range ...

Page 46: ...hms calibration gain calibration value 0x1010 Read an ohms calibration offset calibration value signed 16 bit value 0x1011 Set an ohms calibration offset calibration value 0x1012 Read a 128 Ω gain 32 bit 0x00010000 nominal 0x1013 Set 128 Ω gain 32 bit 0x00010000 0x1014 Read 81 92k gain 32 bit 0x00010000 0x1015 Set 81 92k gain 32 bit 0x00010000 0x1016 Read 9 45 V gain 32 bit 0x00010000 0x1017 Set 9...

Page 47: ...ration memory This operation is executed by the microprocessor at power up automatically This is useful for the user in the event that the calibration memory is accidentally changed and the user wants to recall the factory preset values from the non volatile memory Error Processing Each channel has its own ERROR queue Sending the 0x1024 command to a channel s command register will return an error ...

Page 48: ...nge Voltage mode the voltage is not stable ERROR_MULTIPLE_TEST_SOURCES The user attempted to connect several sources on the Test Bus ERROR_NONVOL_READ There was an error when trying to read the non volatile calibration memory ERROR_NONVOL_WRITE There was an error when trying to write to the non volatile calibration memory ERROR_NONVOL_DEFAULTED There was an error when trying to read the default va...

Page 49: ...he calibrated reference value 9 45 V 0x3007 Read the calibrated reference value 9 45 V 0x3008 Read the calibrated reference value 128 Ω 0x3009 Read the calibrated reference value 81 92 kΩ 0x300A Read self test measurement values 0x300B Turn SYSFAIL ON for diagnostic purposes only 0x300C Turn SYSFAIL OFF just for diagnostic purposes 0x300D Read the calibrated reference value 0 1177 V 0x300E Read th...

Page 50: ...x5502 After issuing each of the above commands the user must wait until the command is executed before issuing the next one When the second 0x5502 command is done it means the new data has been moved into FLASH memory To change the firmware for the second FPGA U20 the new file that needs to be programmed into FLASH is uploaded at offset address 0x000000 Then the following three commands must be is...

Page 51: ...16 bits registers located at offsets 0xC0005C the MS Most Significant bits bits D24 16 and 0xC0005E the LS Least Significant bits bits D15 D0 The Sample Rate register for Channel 4 is similar starting at offset 0xAC Method 1 Make two 16 bits writes For low speed Channel 2 Write 0x0012 to Base address 0xC0005C Write 0xC4B0 to Base address 0xC0005E For high speed Channel 4 Write 0x00E1 to Base addre...

Page 52: ...ple Points Pre Trigger Points Note Pre Trigger Points must be less than Sample Points Pre Trigger Points Sample Points Example 4 Setting Channel 2 to Delay Acquisition by 1 500 000 Samples The acquisition of samples starts when a trigger point is met or when a trigger is forced by setting the corresponding Force bit If the acquisition is to be triggered by a trigger event signal trigger external t...

Page 53: ...ue by the maximum value allowed in the Timeout Counter register and round it up to the next highest value available TIMEOUT BASE CLOCK TIMEOUT VALUE 213 1 2 5 s 8191 0 305 ms The nearest Timeout Base Clock available which is greater than or equal to 0 305 ms is 1 ms Set the TOSEL bits in the Timeout register to 010 To determine the value for the Timeout Counter divide the desired Timeout value by ...

Page 54: ...VXI Technology Inc 54 SVM2608 Programming ...

Page 55: ...eRead16 channel VmeAddress 0x28 Api_Result printf MSB1 02x n data regRdata 0 data data VmeRead16 channel VmeAddress 0x2a Api_Result printf MSB0 02x n data regRdata 1 data data VmeRead16 channel VmeAddress 0x2c Api_Result printf LSB1 02x n data regRdata 2 data data VmeRead16 channel VmeAddress 0x2e Api_Result printf LSB0 02x n data regRdata 3 data now shuffle the bytes dblData data 0 byte regRdata ...

Page 56: ...VXI Technology Inc 56 SVM2608 Appendix A ...

Page 57: ... 33 40 43 logical address 23 24 LSB least significant bit 25 26 M measurement commands 47 50 message based 27 module base address 28 36 module installation 26 MSB most significant bit 25 26 O offset resistance measurements 48 offset value 24 P P F LED 19 Parylene 19 pin locations 20 power 23 pre trigger points register 43 R register address 28 register address example 36 register offset 28 36 regi...

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