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EX10xxA Programming
107
When linked as a limit event, a DIO channel will be cleared at the beginning of a new acquisition.
Its state will then be updated with each scan according to the programmed limit evaluations. By
default, the cleared state is low, but can be set on a per channel basis to be high through the
vtex10xxA_set_dio_limit_event_invert
function. Similarly, the default operation for each channel
is non-latch mode, but can be set on a per channel basis to be latch mode through the
vtex10xxA_set_dio_limit_event_latch
function. In latch mode, a transition out of the cleared state
would remain, regardless of future limit evaluations, until it is cleared at the beginning of a new
acquisition.
The
current
state
of
the
DIO
limit
event
mechanism
is
queried
with
the
vtex10xxA_get_dio_limit_event_invert
and
vtex10xxA_get_dio_limit_event_latch
C
ONFIGURE THE
T
RIGGER
M
ODEL
The EX10xxA supports a full function trigger model with a separate arm source and trigger source
event structure. In summary, an acquisition sequence is enabled with a trigger initialize function.
Scanning is then initiated upon the receipt of the programmed arm source event followed by the
receipt of the programmed trigger source event. Trigger and arm source events can be independently
programmed from a variety of sources including Immediate, Timer, Digital I/O, and the Trigger
Bus.
Configure the ARM event system
The ARM source is configured with the
be specified to be any combination of LXI Trigger Bus channel transitions or levels, Digital I/O
channel transitions or levels, LXI LAN event transitions or levels and Timer ticks, or simply be set
to Immediate. If multiple sources for an ARM event are specified, they are logically combined as
follows:
ARM event = [(Timer tick event) AND (LXI alarm event) AND (LAN event) AND (Digital I/O event) AND (Trigger
Bus event)]
Within each digital hardware port, it is also possible to select multiple channels and multiple
conditions for a specific channel. In that case, they are logically combined as follows:
Digital I/O event = (Ch 7 events) AND (Ch 6 events) … AND (Ch 0 events)
Finally, within each channel, the four event conditions of Pos. Edge, Neg. Edge, Pos. Level, and
Neg. Level are OR’ed together.
As an example, if a Digital I/O event is specified to be a combination of a Pos. Level on channel 3,
a Pos. Edge on channel 6, and a Neg. Edge on channel 6, the event will be satisfied when a Pos.
Level on channel 3 occurs simultaneously with a Pos. Edge or a Neg. Edge transition on channel 6.
While the Digital I/O event structure was used as an example, the Trigger Bus event structure
operates in the same manner.
This function accepts the following parameters:
an array of four 8-bit values representing the enabling of events from any of the 8 channels of
the trigger bus. The order of the values is: positive edge, negative edge, positive level,
negative level. Each value is specified in either decimal (0 through 255) or hex (0x00 through
0xFF). Within the 8-bit field, the MSB corresponds to LXI Trigger Bus (VTB) channel 7 and
the LSB corresponds to LXI Trigger Bus (VTB) channel 0.
Summary of Contents for EX1000A
Page 28: ...VTI Instruments Corp 28 EX10xxA Introduction EX1044 DIAGRAM ...
Page 29: ...www vtiinstruments com EX10xxA Introduction 29 FIGURE 1 5 EX1044 TABLE TOP USAGE ...
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