Vizio VM60P HDTV10A, Service Manual

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CONFIDENTIAL – DO NOT COPY Page 8-
10
File No. SG-0214
Two-Wire
master serial protocol
The two-wire protocol consists of a serial clock MSTR_SCL and bi-directional serial data line
MSTR_SDA. The FLI8668 acts as bus master and drives MSTR_SCL and either the master
or slave can drive the MSTR_SDA line (open drain) depending on whether a read or write
operation is being performed.
There are three isolated Master Serial busses, all driven by a common Master Serial
Controller.
These busses can be independently taken “off-line” or pulled up to different voltages without
affecting the other busses.
The two-wire protocol requires each slave device to be addressable by a 7-bit identification
number.
A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown
in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA
while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to- high transition on
MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).
Figure 8-10 Two-Wire Protocol Data Transfer
Each transaction on the MSTR_SDA is in integer multiples of 8 bits (i.e. bytes). The number of
bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the
most significant bit (MSB) first. After the 8 data bits, the master releases the MSTR_SDA line
and the receiver asserts the MSTR_SDA line low to acknowledge receipt of the data. The
master device generates the MSTR_SCL pulse during the acknowledge cycle. The addressed
receiver is obliged to acknowledge each byte that has been received.