VC_nano_Series.pdf
VC nano Series Smart Cameras Operating Manual
1996-2014 Vision Components GmbH Ettlingen, Germany
A
Appendix A: Block diagram VC nano Series
The image is formed by a high-resolution 5 mega pixel CMOS sensor (VC4012nano & VC6212nano),
a Wide-VGA CMOS sensor (VC6010nano & VC6210nano) or a 1.3 megapixel CMOS sensor
(VC6211nano). The image is then stored in SDRAM memory, which has been increased to 64MB
(VC4012nano) / 128MB (VC6010nano, VC6210nano, VC6211nano & VC6212nano).
Unlike most other Vision Component Smart Cameras, the VC nano Series cameras do not have a
direct video output. However if monitoring of the camera image is required, this can be done by
downloading via Fast Ethernet port to PC and display on screen (see
“Image Transfer” demo
software under “Support -> Customer Area -> Software Utilities”
).
The TMS320C64xx DSP is one of the fastest 32bit DSPs. It features a RISC-like instruction set, up to
8 instructions can be executed in parallel, two L1 cache memories (16 Kbytes each) and a 128 Kbytes
L2 cache on chip. Its high speed 64-channel DMA controller gives additional performance. The DSP
uses fast external SDRAM as main memory. A flash EPROM provides non-volatile memory.
Block diagram VC nano Series
CMOS
Sensor
Trigger In/
Out
Control/
Status Reg.
IOs
128 MB SDRAM
32 MB Flash
Eprom
TMS
C64XX
DSP
Bus Controller
Ethernet
10/100
Ethernet
24V In / Out
24V Trigger In/ Out