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Pin Name Pin Type Function Pin

AVDD_SIF 3.3V Power SIF Power 50
AVDD_AU 3.3V Power Audio Power 70
AVDD_DDR 2.5V Power DDR Power 169, 180, 191, 209,
222, 234, 245
AVDD_LPLL 3.3V Power LPLL Power 160
AVDD_MPLL 3.3V Power MPLL Power 256
AVDD_MEMPLL 3.3V Power PLL Power 201
AVDD_33 3.3V Power ADC Power 6, 32, 46
AVDDL_DVI 1.2V Power DVI Power 248
AVDD_USB 3.3V Power USB Power 250
VDDC 1.2V Power Digital Core Power 53, 89, 102, 163,
194, 230, 247
VDDP 3.3V Power Digital Input/Output Power 78, 113, 133, 147
GND Ground Ground 1, 9, 33, 49, 54, 66,
88, 101, 161, 162,
172, 187, 193, 225,
241, 253
No Connects

Pin Name Pin Type Function Pin

NC No connect. 47, 64, 65, 75

I201,I212 PT5DU281620VP DDRAM (RA)

The PT5DU281620VP is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high
bandwidth.
This Wins 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the
CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both
rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve
very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

I201,I212 HYB25DC256163CE-4 DDR1 (16Mx16) (RB)

The 256-Mbit Double-Data-Rate SGRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
The 256-Mbit Double-Data-Rate SGRAM uses a double-data-rate architecture to achieve high-speed
operation. The doubledata- rate architecture is essentially a 2n prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the
256-Mbit Double-Data-Rate SGRAM effectively consists of a single 2n-bit wide, one clock cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR SGRAM during Reads and by the memory
controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for
Writes.
The 256-Mbit Double-Data-Rate SGRAM operates from a differential clock (CK and CK; the crossing
of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address
and control signals) are registered at every positive edge of CK. Input data is registered on both edges
of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.Read and
write accesses to the DDR SGRAM are burst oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits
registered coincident with the Active command are used to select the bank and row to be accessed. The
address bits registered coincident with the Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SGRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An
Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the
end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR
SGRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row
precharge and activation time.