![background image](http://html1.mh-extra.com/html/viewsonic/ve510-1/ve510-1_service-manual_1021029021.webp)
technique is also used to reduce the number of preamplifiers. Two identical 8bit ADC
converters are used to increase the throughput of sub ranging ADC to one conversion per
clock cycle.
Each ADC operates in two-step sub range, i.e. coarse (3 bits) and fine (5 bits). One to
four interpolations is performed in fine conversion step to minimize the number of
preamplifier and to improve differential non-linearity errors (DNL). In addition, in order to
prevent potential error occurred during coarse conversion, digital error correction
technique is also used.
Clock Re-Generator Functional Block Diagram
FIG3-3 Clock Re-Generator
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E510+-1
Summary of Contents for VE510+-1
Page 10: ...3 Disassembly Assembly Instructions ViewSonic Corporation 7 Confidential Do Not Copy VE510 1...
Page 11: ...ViewSonic Corporation 8 Confidential Do Not Copy VE510 1...
Page 27: ...FIG3 8 Mascot function block ViewSonic Corporation 24 Confidential Do Not Copy VE510 1...
Page 30: ...FIG4 2 MPU Control Block ViewSonic Corporation 27 Confidential Do Not Copy VE510 1...
Page 43: ...ViewSonic Corporation ViewSonic Corporation 40 Confidential Do Not Copy VE510 1...
Page 44: ...ViewSonic Corporation ViewSonic Corporation 41 Confidential Do Not Copy VE510 1...
Page 45: ...ViewSonic Corporation ViewSonic Corporation 42 Confidential Do Not Copy VE510 1...
Page 46: ...8 PCB Layout ViewSonic Corporation 43 Confidential Do Not Copy VE510 1...
Page 47: ...ViewSonic Corporation 44 Confidential Do Not Copy VE510 1...