VIA 693/693A Twin Processor Mainboard
AWARD BIOS SETUP
4-7
4.6
CHIPSET FEATURES SETUP
ROM PCI / ISA BIOS (2A6LGXXX)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Bank 0 / 1 DRAM Timing
: SDRAM 10ns Auto Detect DIMM / PCI Clk : Enabled
Bank 2 / 3 DRAM Timing
: SDRAM 10ns Spread Spectrum
: Disabled
Bank 4 / 5 DRAM Timing
: SDRAM 10ns CPU Host Clock (CPU/PCI)
: Default
SDRAM Cycle Length
: 3
:
DRAM Clock
: CPU CLK
Memory Hole
: Disabled
Read Around write
: Disabled
Concurrent PCI / Host
: Disabled
System BIOS Cacheable
: Disabled
Video RAM Cacheable
: Disabled
AGP Aperture Size
: 64M
AGP-2X Mode
: Enabled
OnChip USB
: Enabled
USB Keyboard Support
: Disabled
ESC : Quit
:
Select Item
F1 : Help
PU/PD/+/- : Modify
F5: Old Values
(Shift)F2 : Color
F7 : Load Setup Defaults
Fig. 4-5 CHIPSET FEATURES SETUP screen.
WARNING :
The selection fields on this screen are provided for the professional
technician who can modify the Chipset features to meet some specific
requirement. If you do not have the related technical background, do
not attempt to make any change except the following items.
Bank 0/1, 2/3, 4/5 DRAM Timing
This item allows you determine the type of timing the system uses when reading or
writing to the SDRAM.
SDRAM Cycle Length :
(default Setting : 3)
This field sets the CAS latency timing of the memory subsystem.
The Choice: 2, 3.
