EPIA
EPIA
EPIA
EPIA-
--
-M720
M720
M720
M720 User Manual
User Manual
User Manual
User Manual
78
6.23.
Frequency/Voltage Control
Current DRAM Frequency
Frequency/Voltage Control
DRAM Clock
Current FSB Frequency
100 MHz
DRAM Timing
533 MHz
[By SPD]
[Auto By SPD]
DRAM Init Method
[Force Software]
DRAM REMAP
[Enabled]
Spread Spectrum
[+/-0.1%]
Phoenix - AwardBIOS CMOS Setup Utility
Item Help
Menu Level
ESC: Exit
F5: Previous Values
: Move
F10: Save
Enter: Select
+/-/PU/PD: Value
F1: General Help
F7: Optimized Defaults
6.23.1.
DRAM Clock
This chipset supports synchronous and asynchronous mode between host
clock and DRAM clock frequency.
Settings: [By SPD, 400 MHz, 533 MHz]
6.23.2.
DRAM Timing
Settings: [Auto By SPD]
6.23.3.
DRAM Init Method
Settings: [Auto: Hardware Init, Force software]
6.23.4.
DRAM REMAP
Settings: [Disabled, Enabled]
6.23.5.
Spread Spectrum
When the mainboard's clock generator pulses, the extreme values (spikes) of
the pulses create EMI (Electromagnetic Interference). The Spread Spectrum
