Vertex Standard VX-820 series, Service Manual

Page: 9 / 42

9
Circuit Description
oscillator Q1051 ( 2SC4227 ) in the VCO generates a
frequency between 134 and 174 MHz (the actual
transmitting frequency). The output from the oscil-
lator is amplified by buffer amplifier
Q1040
( 2SC5005 ) and becomes the output of the VCO. The
output from VCO is divided: one part is amplified
by
Q1049 ( 2SC5005 ) and fed back to the PLL IC at
pin 5. The other is amplified by Q1032 (
2SC5005
)
and, in case of the reception, it is fed via D1023
(
DAN222
) to the mixer as the 1st local signal. On
transmit, it is fed via D1023 ( DAN222 ) to buffer
amplifire Q1027 (
2SC3356
), and passed through the
final amplifier driver Q1024 ( 2SK2375 ) to the final
amplifier Q1019 (
2SK2376
).
3-4-2. VCV (Varactor Control Voltage) Control
The tuning voltage (VCV) of the VCO establishes
the lock range of the VCO by controlling the anode
of a varactor diode using a negative voltage and the
control voltage from PLL IC
Q1068 (
SA7025DK
). The
negative voltage is fed to the varactor diode after
c o n ve r s i o n t o a n e g a t i ve va l u e a t
Q 1 0 3 0
( NJM2130F ), using the output voltage of the D/A
converter, Q1020 ( M62364FP ).
3-4-3. PLL
The PLL IC Q1068 ( SA7025DK ) consists of a refer-
ence divider, main divider, phase detector, charge
pumps and a fractional accumulator. The reference
frequency from TCXO is applied to pin 8 of the PLL
IC Q1068 ( SA7025DK ) and is divided by the refer-
ence divider. This IC is a decimal point dividing PLL
IC, and the dividing ratio becomes 1/8 of the usual
PLL frequency step. Therefore, the output of refer-
ence divider is 8 times the frequency of the channel
step. For example, when the channel steps are set to
5 kHz, the output of reference divider becomes 40
kHz. The feedback signal from the VCO applied to
5 pin of the PLL IC
Q1068 ( SA7025DK ) is divided
according to the dividing ratio so as to become the
same frequency as that of the output of reference
divider. These two signals are compared by the
phase detector, and a phase difference pulse is gen-
erated. The phase difference pulse and the pulse
from the fractional accumulator pass through the
charge pumps and low-pass filter, producing a DC
voltage (VCV) to control the VCO. The oscillation
frequency of the VCO is therefore locked via the
control of this DC voltage. The PLL serial data from
the CPU
Q1067 (
LC87F5BP6A
) is sent with three
lines of data: SDO (pin 20), SCK (pin 22) and PSTB
(pin 27). The lock condition of the PLL is sent from
the UL (pin 17) terminal, and UL becomes “High”
at the time of a proper lock condition and becomes
“Low” at the time of an unlocked condition. The
CPU always watches over the UL condition, and
when it becomes “Low” (unlocked condition), the
CPU
Q1067 ( LC87F5BP6A ) prohibits transmission
and reception.