VersaLogic VL-EPM-31, Hardware Reference Manual, Page: 40 / 77

Multi-purpose I/O
EPM-31 Hardware Reference Manual
39
Table 8 provides the pinout of the user I/O connector.
Table 8: J4 I/O Connector Pinout and Pin Orientation
Pin Signal Pin Signal
1 +5 V 2 GND
3 USB0_P 4 USB1_P
5 USB0_N 6 USB1_N
7 +5V 8 GND
9 USB2_P 10 USB3_P
11 USB2_N 12 USB3_N
13
+3.3 V ( Note 1 )
14 GND
15 SPKR# 16 PLED#
17 PWR_BTN# 18 RST_BTN#
19 GND 20 GND
21 I2C Clock 22 V_BATT
23 I2C Data 24 RETURN_BATT
25 GND 26 GND
27 FPGA GPIO1 28 FPGA GPIO2
29 FPGA GPIO3 30 FPGA GPIO4
31 GND 32 GND
33 FPGA GPIO5 34 FPGA GPIO6
35 FPGA GPIO7 36 FPGA GPIO8
37 +3.3 V ( Note 2 ) 38 GND
39 ETH0 LED 40 ETH1 LED
Notes:
1. This 3.3 V power goes off in sleep modes. The SPKR# uses this power as should the
PLED# (there is no requirement for PLED# to use this power, but the CBR-4005
paddleboard does).
2. This 3.3 V power can be turned on our off similar to the 3.3V power to the Mini Card via
the FPGA (can go off in sleep modes or always stay on; by default it goes off in sleep
modes). It is used for the 10
kΩ pullup resistor power on the 8x GPIOs and usually for the
2x Ethernet LEDs, however, the Ethernet LEDs can be powered by a 3.3 V power source.
C
ABLING
An adapter cable, part number CBR-4005A, is available for connecting the CBR-4005B
paddleboard to the EPM-31. This is a 12-inch, Pico-Clasp 40-pin to 40-pin cable
If your application requires a custom cable, the following information will be useful:
EPM-31 Board Connector Mating Connector
Molex 501571-4007 Molex 501189-4010
I
2
C
Pins 21 and 23 of the J4 User I/O connector connect to the first of the seven I
2
C ports on the Intel
Atom “Bay Trail” processor. The EPM-31 has a 3.3 V I
2
C interface. The required pullups for this
interface are included in the EPM-31 design. The 3.3 V power for this interface is the same as
that used for the digital I/O interface. By default, this power is turned off when the processor is
in a sleep state.