Base Board SPI Registers
SPX-5 Reference Manual
14
SPI
D
ATA
R
EGISTERS
SPIDATA0 (READ/WRITE) 1DAh
D7
D6
D5
D4
D3
D2
D1
D0
MSbit
LSbit
SPIDATA1 (READ/WRITE) 1DBh
D7
D6
D5
D4
D3
D2
D1
D0
MSbit
LSbit
SPIDATA2 (READ/WRITE) 1DCh
D7
D6
D5
D4
D3
D2
D1
D0
MSbit
LSbit
SPIDATA3 (READ/WRITE) 1DDh
D7
D6
D5
D4
D3
D2
D1
D0
MSbit
LSbit
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this
register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to
begin an SPI bus transaction. Increasing frame sizes from 8-bit use the lowest address for the
least significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit
of SPIDATA3 is sent first, and received data will be shifted into the LSbit of the selected frame
size set in the SPILEN field. When LSBIT_1ST = 1, the LSbit of the selected frame size is sent
first, and the received data will be shifted into the MSbit of SPIDATA3.
