VCSBC64XX_HW.pdf – Hardware Documentation VCSBC64XX Smart Cameras
6
2 Basic
Structure
The image is formed by a high-resolution progressive scan CCD sensor. One channel of video input is
digitized. The image is stored in SDRAM memory using one of the 64 DMA channels (EDMA).
Unlike most other Vision Component Smart Cameras, the VCSBC64XX does not have a direct video
output. However if monitoring of the camera image is required, this can be done by downloading via
Fast Ethernet port to PC and display on screen.
The TM DSP is one of the fastest 32bit DSPs. It features a RISC-like instruction set, up to 8
instructions can be executed in parallel, a L1 cache memory (32 Kbytes) and a 256 Kbytes L2 cache
on chip. Its high speed 64-channel DMA controller gives additional performance. The DSP uses fast
external DDR-SDRAM as main memory. A flash EPROM provides non-volatile memory.
Block diagram VCSBC64XX Smart Camera
CCD -
Sensor
PGA
CDS
A/D Con-
verter
RS232C
256 MB
DDR-SDRAM
Trigger In/ Out,
Encoder, PLC
I/Os
RS232
FPGA
DM648
DSP
Ethernet
Ethernet
32 MB Flash
EPROM
©
1996-2011 Vision Components GmbH Ettlingen, Germany
