Vaisala MPU112, Technical Reference, Page: 27 / 55

Chapter 8 ____________________________________________________________ Technical Data
VAISALA _______________________________________________________________________ 25
Connector Signal Layout
System connector is a 220-pin, 5-row female Connector.
Table 3 System Connector Signal Layout
Pin/Row a I/O b I/O c I/O d I/O e I/O
1 GND GND GND GND GND
2
3 TS1 I/O TS2 I/O TS3 I/O TS4 I/O TS5 I/O
4 VGAR O VGAG O VGAB O AGND VGAHX O
5 VGAVX O KBDATA I/O KBCLK O MSDATA I/O MSCLK O
6 USBCLK I/O USBDATA I/O RESDRV# I
7 HD7 I/O HD8 I/O HD6 I/O HD9 I/O HD5 I/O
8 HD10 I/O HD4 I/O HD11 I/O HD3 I/O HD12 I/O
9 HD2 I/O HD13 I/O HD1 I/O HD14 I/O HD0 I/O
10 HD15 I/O HDRQ O HDWR# O HDRD# O HDRDY I
11 HDACK# O HDIRQ I HDIOC16 I/O HDA1 O PDIAG# I/O
12 HDA0 O HDA2 O HCS0 O HCS1 O DASP# I/O
13
14
15
16
17
18 ARC+ I/O ARC- I/O
19 TXD6 O
20 RXD6 I
21 TXD5 O
22 RXD5 I
23 GND GND GND GND GND
24 E3RX+ I E3RX- I GND E3TX+ O E3TX- O
25 GND GND GND GND GND
26 E4RX+ I E4RX- I GND E4TX+ O E4TX- O
27 GND GND GND GND GND
28 TXD3A O TXD3B O TXD3C- O TXD3C+ O
29 RXD3A I RXD3B I RXD3C- I RXD3C+ I
30 TXD2 O DTR2 O RTS2 O ARC+ I/O
31 RXD2 I DSR2 I CTS2 I ARC- I/O
32 TXD1 O TXD4 O OPX1 O OPX2 O
33 RXD1 I RXD4 I IPX1 I IPX2 I
37 MRES# I
38 JTDOUT O JTCKIN I JTDIN I JTMSIN I
39 TESTX# I
40
41 +VSTBY FWGATE# O FHDSEL# O
42 +3.3 V +3.3 V +3.3 V +3.3 V +3.3 V
43 FMTR0# O FDR0# O FDIR# O FSTEP# O FWDATA# O
44 +5 V +5 V +5 V +5 V +5 V
45 FINDEX
R0#
I FTRK0
R1#
I FWRPRT
R2#
I FRDATA
R3#
I FDCHG
R4#
I
46 GND
47 GND GND GND GND GND