TECHNICAL REFERENCE___________________________________________________________
12 __________________________________________________________________ M210829EN-A
- The D14 output CONFD goes to high level to indicate properly
completed configuration cycle.
- The D14 enters user mode and starts to operate according to the
loaded code.
The initial code allows the operating system of the Computer Module
to recognize the logic devices in the PLD. The code loading continues
when the boot sequence of the Computer Module is completed.
Then the final code is loaded as follows:
- The select signals PLDMSEL0, PLDMSEL1 of the programming
mode are set to high level to select the passive parallel
configuration mode.
- The signal PLDCONFIG# is pulsed low to start the configuration.
- The PLD code is loaded in byte serial format using control signals
PLDCS#, IOWR#, IORD# and data bus PLDD0CONF (data bit 0),
SD01, ..., SD07 (data bit 7).
- The D14 output CONFD goes to high level to indicate properly
completed configuration cycle.
The signal PLDD0CONF is used for data bit 0 only during
configuration. Later in the operation, the signal SD00 is used as data
0.
The resistors R64, R65, R79 and R73, R90, R94 are used to allow
overriding of D16 outputs.
The PLD D14 is used to implement the main timing, control, and
interface logic functions in the MPU112.
The PLD D14 includes the following main functions:
ISA Bus Interface
ISA bus control, data, and address signals are connected from the
CPU ISA bus to the PLD for ARCNET, additional serial channels,
and general purpose I/O functions.
Address Decoders
Address lines SA00 ... SA11 together with I/O control signals IOWR#
and IORD# are used to select the desired control functions in the PLD.