background image

15

Pinning:

2,8,24,42,55

Supply volt ( 

V

SS=0V )

54.

System clock 1

9,25,41,56

Supply volt ( 

V

DD=3.3V )

17,..,10 Data output UV

36,52,58

Supply volt ( 

V

SS=0V )

7,..,3;1;64;63

Data output Y

35,51,53,57,59

Supply volt ( 

V

DD=3.3V )

62

Horz active video out

43,..,50

Data input Y

61

V-Sync out / Ext V-Sync

31,..,34;37,..,40 Data input UV

60

H-Sync out / Ext H-Sync

30

System reset.

18

Interlace signal vert deflection

23

H-Sync input

28

Crystal conn / System clock 2

22

V-Sync input

27

Crystal connection

29

Sync enable input

26

Clock output

21

I2C-Bus data line

19

Test input

20

I2C-Bus clock line

DDP3310:

  It is the display and deflection processor. All the horizontal and vertical stages are driven by this IC.

The last controls such as contrast, brightness and saturation of the actual video signal, OSD and VGA are accomplished

by the blocks in DDP. Tube measurement and SVM controls are also managed by this IC.

Features:

Video processing

– linear horizontal scaling (0.25 … 4)

– non-linear horizontal scaling “panoramavision”

– dynamic peaking

– soft limiter (gamma correction)

– color transient improvement

– programmable RGB matrix

– picture frame generator

– two analog RGB/Fast-Blank inputs

Deflection processing

– scan velocity modulation output

– high-performance H/V deflection

– EHT compensation for vertical / East/West

– soft start/stop of H-Drive

– vertical angle and bow

– differential vertical output

– vertical zoom via deflection

– horizontal and vertical protection circuit

– adjustable horizontal frequency for VGA/SVGA dis-play

Miscellaneous

– selectable 4:1:1/ 4:2:2 YC r C b input

– selectable 27/ 32-MHz line-locked clock input

– crystal oscillator for horizontal protection

– automatic picture tube adjustment (cutoff, white-drive)

– single 5-V power supply

Summary of Contents for FT-81031

Page 1: ...SERVICE MANUAL UNIVERSUM FT 81031 MODEL ...

Page 2: ...z FEATURE BOX 11 VPC32X5 VIDEO PROESSOR 11 CIP3250 12 13 SDA9400 13 14 15 DDP3310 15 16 AK41 CHASSIS MANUALADJUSTMENTS PROCEDURE 17 PRELIMINARY 17 SYSTEM VOLTAGEAJUSTMENT 17 AFCADJUSTMENT 17 FOCUSADJUSTMENT 17 SCREENADJUSTMENT 17 IFADJUSTMENT FOR L MODE 17 AK41 CHASSIS PRODUCTION MODE ADJUSTMENTS PROCEDURE 18 PRELIMINARY 18 HORIZONTALAND VERTICALGEOMETRY ALIGNMENTS 18 V SHIFT 18 V SIZE 18 H SHIFT ...

Page 3: ...ue 5 Ground Blue 6 Audio left input 0 5Vrms 10K 6 Audio left input 0 5Vrms 10K 7 Blue input 0 7Vpp 75ohm 7 Blue input 0 7Vpp 75ohm 8 AV switching input 0 12VDC 10K 8 AV switching input 0 12VDC 10K 9 Ground Green 9 Ground Green 10 10 11 Green input 0 7Vpp 75ohm 11 12 12 13 Ground Red 13 Ground Red 14 Ground Blanking 14 Ground Blanking 15 Red input 0 7Vpp 75ohm 15 16 Blanking input 0 0 4VDC 1 3VDC 7...

Page 4: ...ppression Time n Synchronization and Fixed Frequency Facility n Over and Under voltage Lockout n Switch Off at Mains Under voltage n Mains Voltage Dependent Fold Back Point Correction n Low Power Consumption n Free usable Fault Comparators Pinning 1 OTC Off Time Circuit 2 PCS Primary Current Simulation 3 RZI Regulation and Zero Crossing Input 4 SRC Soft Start and Regulation Capacitor 5 OCI Opto Co...

Page 5: ...r AGC current 2mA 11 Available tuner AGC current Min 0 3V Max 13 5V 12 Video output Min 1 8V Max 2 2V 13 Standard switch Min 0V Max 0 8V 14 L switch Min 0V Max 3 0V 15 IF gain control range 65dB 16 Ground 17 Internal reference voltage 18 FPLL and VCO Min 1mA Max 4mA 19 AFC switch Min 0V Max 0 8V 20 FPLL and VCO Min 1mA Max 4mA 21 FPLL and VCO Min 1mA Max 4mA 22 AFC output 0 7 mA kHz 23 DC supplay ...

Page 6: ... necessary for tuning the open loop frequency of the internal PLL and for stabilising the frequency in closed loop operation The higher the capacitors the lower the clock frequency result The nominal free running frequency should match the centre of the tolerance range between 18 433 and 18 431Mhz as closely as possible By means of standardised I2S interface additional feature processors DPL35xx D...

Page 7: ...rt input 1 in left 65 I S2 data input 32 Analog Shield Ground 2 66 Digital ground 33 Scart input 2 in right 67 Digital power supply 5V 34 Scart input 2 in left 68 ADR clock DOLBY PRO LOGIC PROCESSOR IC DPL3519A The IC DPL3519A processor family is designed to decode Dolby encoded surround sound The IC integrate the complete Dolby Surround Pro Logic decoding on chip without any necessary external ci...

Page 8: ...s n Wide temperature range n No switch ON OFF clicks n Excellent power supply ripple rejection n Low power consumption n Short circuit resistant n High performance high signal to noise ratio high slew rate low distortion n Large output voltage swing Pinning 1 OutputA Voltage swing Min 0 75V Max 4 25V 2 Inverting inputA Vo clip Min 1400mVrms 3 Non inverting inputA 2 5V 4 Ground 5 Non inverting inpu...

Page 9: ...ax 3mA 9 Vcc 12V 10 Input Max 2Vpp Input Current 1mA Max 3mA 11 Input Max 2Vpp Input Current 1mA Max 3mA 12 Ground 13 Output 5 5Vpp Min 4 5Vpp 14 Output 5 5Vpp Min 4 5Vpp 15 Output 5 5Vpp Min 4 5Vpp 16 Output 5 5Vpp Min 4 5Vpp 17 Output 5 5Vpp Min 4 5Vpp 18 Output 5 5Vpp Min 4 5Vpp 19 Ground 20 Input Max 2Vpp Input Current 1mA Max 3mA VIDEO OUTPUT AMPLIFIER STAGE TDA6111Q The TDA6111Q is a video o...

Page 10: ...ters and additional interrupts etc The on chip display unit for displaying Level 1 5 teletext data can also be used for customer defined on screen displays Internal XRAM consists of up to17 Kbytes AK41 has the version without internal ROM This device can support external memory up to 1Mbyte ROM and RAM TVTEXT Controller con tains a data slicer for VPS WSS PDC and TXT an acceleration acquisition ha...

Page 11: ... 3 4 7 One 4 bit I O port with secondary functions P4 0 4 1 4 4 SERIAL ACCESS 32K EEPROM 24LC32 W It is the 32Kbit electrically erasable programmable memory The memory is compatible with the I2C standard two wire serial interface which uses a bi directional data bus and serial clock Features n Single supply with 3 3V operation down to 2 5V n Compatible with I2C extended addressing n 2 wire I2C ser...

Page 12: ...ration and luma chroma inputs in the SVHS applications there are also R G B FB inputs from the PIP module OSD R G B FB inputs from the Megatext IC or from the controller in the case of TV text option While the 50Hz sync signals for PIP are supplied by the VPC3215 the 100Hz sync signals for OSD are supplied by the DDP3310 Control signals for HV stage such as VertQ Vert HDrive EW East West and SVM S...

Page 13: ...Video 2Analog Input 18 Double Output Clock 62 Video 1Analog Input 19 Output Clock 63 Chroma Video 4 Analog Input 20 29 Picture Bus Luma 64 Analog Video Output 26 Ground 65 Analog Shield GND F 27 Not Connected 66 Supply Voltage Analog Front End 30 Main Clock Output 20 25 MHz 67 Signal Ground forAnalog Input 31 Supply Volt 68 Reference Voltage Top Analog 34 Ground CIP3250 The IC is used to interface...

Page 14: ...nal Capacitor 28 Active Video Output 60 Substrate connect to ground 29 Active Video Input 61 Fast Blank Input 30 Front Sync Input 62 Ground Fast Blank 31 I C Clock Input Output 63 Blue U Input 32 I C Data Input Output 64 Ground Blue U 33 35 Picture Bus Priority 65 Green Luma Input 36 43 Chroma Input 66 Ground Green Luma 44 51 Luma Input 67 Red V Input 52 Digital Ground 68 Ground Red V 53 Digital S...

Page 15: ...ncept Decoupling of the input and output clock system possible Scan rate conversion Motion adaptive 100 120 Hz interlaced scan conversion Motion adaptive 50 60 Hz progressive scan conversion Simple static interlaced and progressive conversion modes for 100 120 Hz interlaced or 50 60 Hz progressive scan conversion e g ABAB AABB AA B B AAAA BBBB AB AA Simple progressive scan conversion with joint li...

Page 16: ...tual video signal OSD and VGA are accomplished by the blocks in DDP Tube measurement and SVM controls are also managed by this IC Features Video processing linear horizontal scaling 0 25 4 non linear horizontal scaling panoramavision dynamic peaking soft limiter gamma correction color transient improvement programmable RGB matrix picture frame generator two analog RGB Fast Blank inputs Deflection ...

Page 17: ...Test Pin 12 Select of H Drv Freq Range 39 Reset Input active low 13 Clock Sel 40 5 or 27 32MHz 40 PWM out 14 Clock select 27 32 MHz 41 PWM out 15 Range Switch2 MeasureADC 42 Half Contrast 16 Range Switch1 MeasureADC 43 50 Picture Bus Chroma 17 SenseADC Input 51 Supply Volt Digital Circuitry 18 Ground MADC Input 52 Ground Digital Circuitry 19 Differential Vert Sawtooth Out 53 Sys Clock Input 27 32 ...

Page 18: ...lts TV should automatically tune to a station when search tuning is activated D FOCUS ADJUSTMENT Inputs AC power PAL B G test pattern via RF input Outputs Picture tube drive Display Picture Action Select TV mode and tune to the signal Adjust focus potentiometer the upper pot on the rear side of the FBT transformer for optimum focusing drive E SCREEN ADJUSTMENT Inputs AC power PAL B G Colour Bar te...

Page 19: ...est pattern is horizontally in equal distance both to right and left sides of the picture tube Check and readjust H SHIFT item if the adjustment becomes improper after some other geometric adjustments are done 4 H SIZE Adjust H WIDTH item by pressing cursor left and or cursor right buttons till no under scan condition will happen i e no white bars on the left and right side of the test pattern wil...

Page 20: ...d BGn by cursor up and or cursor down buttons and change the values by cursor left and or cursor right buttons till the following values are read X 285 10 Y 293 10 on the colour analyser 2 RRf GRf BRf Set the values of these items as 62 constant 3 YDF Apply COLOUR BAR test pattern Select YDF item cursor up and or cursor down buttons Adjust YDF by pressing cursor left and or cursor right buttons ti...

Page 21: ...of the PIP frame edges of the PIP EHTHP EHT compensation coefficient for horizontal phase EHTHTC EHT time contant for horizontal phase compensation EHTH EHT compensation coefficient for horizontal amplitude EHTV EHT compensation coefficient for vertical amplitude EHTV TC time contant for control of vertical and horizontal amplitude EHT compenzation 0 means off OSD LEVEL contast level of the OSD IN...

Page 22: ... 5 5 6 6 2 6 5 5 6 1 7 7 8 5 2 0 2 8 0 2 B 6 7 7 7 5 7 2 5 9 5 7 6 7 9 6 6 9 6 6 6 5 7 5 6 9 0 0 8 7 3 5 2 7 8 6 5 6 6 6 7 H U U H V W H U L D O 7 X Q H U 7 0 6 3 3 9 3 3 6 3 6 6 6 5 6 6 2 8 1 2 5 1 9 6 7 1 2 5 7 9 L G H R 6 Z L W F K L Q J 0 D W U L 6 5 7 6 5 7 0 6 3 U R Q W B 9 6 6 6 6 0 2 1 2 1 4 6 6 3 6 0 1 B 5 6 7 5 3 2 1 H Q W H U 6 X U R X Q G 5 5 0 1 B 9 6 7 H W B 9 6 6 B 6 6 9 6 B 6 B 5 6...

Page 23: ...END SHOW AK41 FEATURES AK41 GENERAL BLOCK DIAGRAM FOR ALL PARTS ...

Page 24: ...re Nicam German stereo Built in 2 speakers Volume controlled Headphone output and headphone terminals jacks 2 Left Right speaker sockets DIN Balance control 5 Band equaliser 2 x Euro AV plug Scart 75 Ohm Aerial socket Fastext and Toptext Multipicture Optional Features Multi system reception Pal BG Pal DK PAL I Secam BG Secam DK Secam L L Secam K 16 9 screen aspect ratio Live Picture In Picture 2 T...

Page 25: ...AUSİNG LINE_IN TDA16846 VOLTAGE REG 145V 5V 8V 12V 5V_STBY TDA6111 TDA6111 TDA6111 CRT BOARD VERTICAL STAGE VS2 HS2 VS2 HS2 RGB_OUT SVM LLC1 LLC2 3 MUTE H PROT FLYBACK HS1 VS1 I2C BUS ADRESSES Terresterial Tuner C0 Active Splitter C6 TEA6415 06 MSP 34XX 80 DPL3519 84 VPC3215 8E CIP3250 DC SDA9400 BC DDP3310B BA PIP Tuner C4 SDA9488 D6 SDA SCL RES SOUND BOARD AND AV SWITCHING BOARD TEA6415C Video S...

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