DNx-SL-514 Synchronous Serial Interface Board
Chapter 3
23
Programming with the Low-Level API
May 2018
www.ueidaq.com
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© Copyright 2018
United Electronic Industries, Inc.
3.3.2
Setting the
Baud Rate
Using the PLL
The SL-514 can use on-board phase locked loop (PLL) circuitry to generate the
master output clock baud rate, or alternatively, divide a 66 MHz onboard system
clock to generate the master clock.
This section provides an overview of how to setup the PLL. To use this function,
you must use
L514CFG_CLK_PLL
as the
clock_source
configuration
parameter
(see
Section 3.3.1 on page 21 for configuration options.)
DqAdv514SetPll(
int hd,
// Handle to IOM received from DqOpenIOM()
int devn,
// Board device # inside the IOM chassis
int chan,
// Channel to be configured
float baudrate,
// Desired baud rate
float* &actual_baud);// Actual baud rate
This function returns an
actual_baud
parameter.
To set the baud rate, the user-defined
baudrate
value is used to program the
PLL. The PLL dividers may not be able to produce the exact programmed rate;
in which case, the value closest to the user-programmed rate is used. Users can
check the
actual_baud
parameter to know what baud rate is used.
s_trigger
slave trigger source that allows data to start transmission:
•
L514CFG_TRIG_IMM
: start immediately after enable, transmit when the
data is in the buffer
•
L514CFG_TRIG_GLOBAL
: wait for the global trigger to start
s_Tv
slave tv time delay: see Figure 1-3 on page 8 and refer to Section 1.7.2 on page 9 for
more information.
s_Tp
slave pause time delay setting: see Figure 1-3 on page 8 and refer to Section 1.7.2
on page 9 for more information.
s_Tm
slave transfer timeout/monoflop time setting: see Figure 1-3 on page 8 and refer to
Section 1.7.2 on page 9 for more information.
Table 3-2
SL-514
Configuration Options
Configuration
Parameter
Options
