User’s Manual
23
3-4. Details of the Advanced Chipset Features Setup
Advanced Chipset Feature
DRAM Timing By SPD
: Enabled
DRAM Clock
: Host CLK
SDRAM Cycle Length
: 3
Bank Interleave
: Disabled
Memory Hole
: Disabled
P2C/C2P Concurrency : Enabled
Fast R-W Turn Around :Disabled
System BIOS Cacheable
: Enabled
Video BIOS Cacheable
: Enabled
Frame Buffer Size
: 8M
AGP Aperture Size
: 128M
AGP-4X Mode :Enabled
AGP Driving Control :Auto
OnChip USB
: Disabled
CPU to PCI Write Buffer :Enabled
PCI Dynamic Bursting :Enabled
PCI Master 0 WS Write :Enabled
PCI Delay Transaction :Disabled
PCI#2 Access #1 Retry :Enabled
AGP Master 1 WS Write :Disabled
AGP Master 1 WS Read :Disabled
SDRAM Cycle Length
This item sets the CAS latency timing.
Video BIOS Cacheable
When enabled, the Video BIOS cache will cause access to video BIOS addressed at
C0000H to C7FFFH to be cached, if the cache controller is also enabled.
System BIOS Cacheable
Enabling this selection allows access to the system BIOS ROM addressed
F0000H-FFFFFH to be cached, provided the cache controller is enabled.
Memory Hole At 15Mb Addr.
In order to improve performance, certain space in memory is reserved for ISA cards.
This memory must be mapped into the memory space below 16MB.
