Ultrasound Technologies Fetatrack 310, Service Manual

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Circuit Description
Fetatrack310 Service Manual Issue3
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Microprocessor Circuit
The microprocessor circuit is arranged around MC68HC812 (U8) a fast second
generation central processing unit (CPU). When power is applied to the circuit a
monitor circuit waits for the power rail to become stable and then 100 ms later
takes the reset on the CPU high (logic 1) to 5 v. This starts the CPU working by
reading the bytes at the very top of its memory map from the EPROM (ROM)
(U9). This shows the CPU the start position in ROM from which to start
executing. This sets up all the peripheral devices, which includes an interrupt
timer, starts the system clock which consists of interrupts from the cpu to the
watchdog ic at the rate of 1 every millisecond. As all functions are time dependant
nothing starts without this clock. The CPU now reads all the preset variables
from the battery protected RAM within the real time clock (U13). The battery source
is a lithium 3.6 v cell (B1) with a nominal life of 10 years.
After the CPU has loaded the variables it rums a system check for any internal
problems which are reported on the system display.
Selection of the individual devices is controlled by cpu internal the chip select
circuits.
Most analogue signals eventually require digital signal processing for
display, chart recording or digital transmission, the signals are presented to CPU,
where an internal 8 bit A/D converter with an 8 way multiplexed input converts the
signals to digital form. The converter accepts unipolar signals of 0 - 5 v..
The CPU interfaces with the display and keyboard circuit using on chip peripheral
interface , as well as detecting selection of ultrasound and the presence of an
Event keypress.
Printer Interface
A proportion of the micro-circuit is dedicated to printer interface and control,
the primary interface circuit contains timers, serial drivers and peripheral drivers.
The principal of operation of the printhead and motor drive circuit is as follows :
Data is decoded by the software into bit positions within the allowable area of
the printhead . This data is then passed in serial form with a clock signal into the
printheads serial buffer. The data is latched by a pulse from the cpu via CMOS
buffer, this gives added protection in the case of device failure. Data is then
burnt onto the printhead by strobes 1 to 4 from the cpu which last less than 1 mS .
The data is passed to the Display and Recorder interface board via ribbon cables
J6 and J7. Printhead data is buffered on the interface board by U1 before being
passed directly to the printhead. (J1)
Under normal conditions with the printer OFF there is no supply connected to the
printhead or chart motor. Only when printing is requested does the cpu turn on the
24VDC supply.
The cpu also drives the chart recorder stepper motor via the high current microstep
interface. The data is again passed to the Display and Recorder interface board via
ribbon cables J6 and J7, after first being processed by microstep controller U23.
The signals generated are turned in to phase data by driver U2 on the interface
board before energising the coils of the motor. (J4)