Ublox XPLR-HPG-2, User Manual

Page: 18 / 28

UBX-22039292 - R01 Module configuration Page 18 of 28
C1-Public
NINA-W106
pin
ESP32 GPIO Signal function Available from Notes
22 GPIO1 CDC_TX - USB CDC RX
23 GPIO3 CDC_RX - USB CDC TX
24 GPIO4 GPIO4 / CAN_RX J2-2 Needs external CAN transceiver
25 GPIO2 LED / GPIO2 J2-1 Host status LED (blue)
27 GPIO0 BOOT / GPIO0 J2-4 BOOT button, USB CDC RTS/CTS.
See also Auto reset circuit .
28 GPIO5 GPIO5 / CAN_TX J2-3 Needs external CAN transceiver.
29 GPIO18 uSD_SCK / SCK J10-3 SPI CLK connected to microSD.
31 GPIO14 LTE_DCD J5-4, J11-2
(unpopulated
JTAG, bottom side)
UART to LTE. See LARA-R6001D LTE cat 1 modem .
JTAG JTMS. See JTAG connector
32 GPIO15 LTE_DTR J5-5, J11-6
(unpopulated
JTAG, bottom side)
UART to LTE. See LARA-R6001D LTE cat 1 modem
JTAG JTDO. See JTAG connector .
34 ADC34/GPI35 SYS_OUT_MON - Analog input, relative to SYS_OUT/Battery Voltage.
35 GPIO13 LTE_DSR J5-2, J11-4
(unpopulated
JTAG, bottom side)
UART to LTE. See LARA-R6001D LTE cat 1 modem
JTAG JTCLK. See JTAG connector .
36 GPIO12 LTE_RI J5-3, J11-8
(unpopulated
JTAG, bottom side)
UART to LTE. See LARA-R6001D LTE cat 1 modem
JTAG JTDI. See JTAG connector .
Table 1: NINA-W106 pinout
For further information, see also the NINA-W10 data sheet [1] and system integration manual [2] .
4.1.3 Auto reset circuit
XPLR-HPG-2 board includes a typical auto reset circuit that connects to the BOOT0 and RESET pins
of NINA-W106, as shown in Figure 13 . The circuit enables the programming tools (like
esptool.py
) to
assert the DTR and RTS control lines of the USB to Serial converter (CP2102N) and set NINA-W106
on the serial bootloader mode. More information can be found in the Espressif Automatic Bootloader
documentation
[14] .
Figure 13: Auto reset circuit
☞
Capacitor C41 is not mounted on the C214 board but can be added in the application design – if
needed.