TIM-5H
-
Hardware
Integration
Manual
Design-In
GPS.G5-MS5-07015-A-1
u-blox
proprietary
Page 13
your position is our focus
2.4 I/O Pins
2.4.1 RESET_N
As
with
ANTARIS
4
versions,
TIM-5H
comes
equipped
with
a
RESET_N
pin.
Driving
the
signal
low
at
RESET_N
activates
a
hardware
reset
of
the
system.
Unlike
LEA-4x
modules,
RESET_N
is
not
an
I/O
with
TIM-5H.
It
is
only
an
input
and
will
not
reset
external
circuitry.
Use
components
with
open
drain
output
(i.e.
with
buffer
or
voltage
supervisor
).
There
is
an
internal
pull
up
resistor
of
3k3
to
VCC
inside
the
module
that
requires
that
the
reset
circuitry
can
deliver
enough
current
(e.g.
1mA).
RESET_N
is
provided
with
TIM-5H
to
provide
Reset
compatibility
with
ANTARIS
4
versions.
Future
TIM
models
may
not
include
this
pin
and
it
is
therefore
not
recommended
to
use
it.
The
preferred
option
for
executing
a
hardware
reset
is
to
send
software
commands
(CFG-RST).
Do
not
drive
RESET_N
high.
2.4.2 EXTINT0
EXTINT0
is
an
external
interrupt
pin
with
fixed
input
voltage
thresholds
independent
of
VCC
(see
the
TIM-5H
Data Sheet
[3]).
Leave
open
if
unused.
2.4.3 AADET_N
AADET_N
is
an
input
pin
and
is
used
to
report
whether
an
external
circuit
has
detected
a
external
antenna
or
not.
Low
means
antenna
has
been
detected.
High
means
no
external
antenna
has
been
detected.
See
chapter
for
an
implementation
example.
