Ublox SARA-N4 Series, System Integration Manual

Page: 106 / 157

SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R11 Design-in Page 106 of 157
☞
If the USB interface is enabled, the module does not enter the low power deep sleep mode: the external
USB VBUS supply voltage needs to be removed from the
VUSB_DET input of the module to let it enter
the Power Saving Mode defined in 3GPP Rel.13.
☞
If the USB interface pins are not used, they can be left unconnected on the application board, but it is
strongly recommended to provide accessible test points directly connected to the USB interface pins
(
VUSB_DET , USB_D+ , USB_D- ).
2.6.2.2 Guidelines for USB layout design
The USB_D+ / USB_D- lines require accurate layout design to achieve reliable signaling at the high speed
data rate (up to 480 Mb/s) supported by the USB serial interface.
The characteristic impedance of the USB_D+ / USB_D- lines is specified by the Universal Serial Bus Revision
2.0 specification [4] . The most important parameter is the differential characteristic impedance applicable
for the odd-mode electromagnetic field, which should be as close as possible to 90

differential. Signal
integrity may be degraded if PCB layout is not optimal, especially when the USB signaling lines are very
long.
Use the following general routing guidelines to minimize signal quality problems:

Route USB_D+ / USB_D- lines as a differential pair

Route USB_D+ / USB_D- lines as short as possible
 Ensure the differential characteristic impedance (Z
0
) is as close as possible to 90 
 Ensure the common mode characteristic impedance (Z
CM
) is as close as possible to 30 

Consider design rules for USB_D+ / USB_D- similar to RF transmission lines, being them coupled
differential micro-strip or buried stripline: avoid any stubs, abrupt change of layout, and route on clear
PCB area
Figure 49 and Figure 50 provide two examples of coplanar waveguide designs with differential characteristic
impedance close to 90

and common mode characteristic impedance close to 30

. The first transmission
line can be implemented in case of 4-layer PCB stack-up herein described, the second transmission line can
be implemented in case of 2-layer PCB stack-up herein described.
35
µ
m
35 µ m
35
µ
m
35
µ
m
270
µ
m
270 µ m
760
µ
m
L1 Copper
L3 Copper
L2 Copper
L4 Copper
FR-4 dielect ric
FR-4 dielect ric
FR-4 dielect ric
350 µ m 40 0 µ m 40 0 µ m 350 µ m 40 0 µ m
Figure 49: Example of USB line design, with Z
0
close to 90  and Z
CM
close to 30  , for the described 4-layer board layup