SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26
Design-in
Page 119 of 217
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It is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna
manufacturer regarding correct installation and deployment of the antenna system, including PCB layout
and matching circuitry.
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Further to the custom PCB and product restrictions, the antenna may require tuning to obtain the
required performance for compliance with the applicable certification schemes. It is recommended to
ask the antenna manufacturer for the design-in guidelines related to the custom application.
In both cases, selecting an external or an internal antenna, observe these recommendations:
Select an antenna providing optimal return loss (or V.S.W.R.) figure over all the operating frequencies.
Select an antenna providing optimal efficiency figure over all the operating frequencies.
Select an antenna providing appropriate gain figure (i.e. combined antenna directivity and efficiency figure)
so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified in some
countries (e.g. by FCC in the United States, as reported in section 4.2.2).
For the additional specific guidelines for SARA-G340 ATEX, SARA-G350 ATEX, SARA-U201 ATEX and
SARA-U270 ATEX modules integrated in potentially explosive atmospheres, see section 2.14.
2.4.1.2
Guidelines for antenna RF interface design
Guidelines for ANT pin RF connection design
Proper transition between the
ANT
pin and the application board PCB must be provided, implementing the
following design-in guidelines for the layout of the application PCB close to the pad designed for the
ANT
pin:
On a multi layer board, the whole layer stack below the RF connection should be free of digital lines
Increase GND keep-out (i.e. clearance, a void area) around the
ANT
pad, on the top layer of the application
PCB, to at least 250 µm up to adjacent pads metal definition and up to 400 µm on the area below the
module, to reduce parasitic capacitance to ground, as described in the left picture in Figure 56
Add GND keep-out (i.e. clearance, a void area) on the buried metal layer below the
ANT
pad if the top-layer
to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance to ground, as described
in the right picture in Figure 56
Min.
250 µm
Min. 400 µm
GND
ANT
GND clearance
on very close buried layer
below ANT pad
GND clearance
on top layer
around ANT pad
Figure 56: GND keep-out area on the top layer around ANT pad and on the very close buried layer below ANT pad
