LENA-R8 series - System integration manual
UBX-22015376 - R02
Design-in
Page 87 of 116
C1-Public
•
Optimize the mechanical design of the application device, the position, orientation and mechanical
fixing (for example, using rubber gaskets) of speaker and microphone parts in order to avoid echo
interference between the downlink path and uplink path.
•
For an external audio device providing differential speaker / receiver output, route the speaker
signal lines as a differential pair embedded in ground up to reduce differential noise pick-up. The
balanced configuration will help reject the common mode noise.
•
Cross other signals lines on adjacent layers with 90° crossing.
•
Place the bypass capacitor for RF close to the speaker.
2.8
Cellular General Purpose Input/Output (GPIO)
2.8.1.1
Guidelines for GPIO circuit design
A typical usage of LENA-R8 series
modules’ GPIOs can be the following:
•
Network indication provided over
GPIO1
pin (see
•
GNSS supply enable function provided by the
GPIO2
pin (see section
•
GNSS Tx data ready function provided by the
GPIO3
pin (see section
•
SIM card detection provided over the
GPIO5
pin (see
in section
LENA-R8 series
GPIO1
R1
R3
3V8
Network Indicator
R2
16
DL1
T1
Figure 66: Application circuit for network indication provided over GPIO1
Reference
Description
Part number - manufacturer
R1
10 k
Resistor 0402 5% 0.1 W
Various manufacturers
R2
47 k
Resistor 0402 5% 0.1 W
Various manufacturers
R3
820
Resistor 0402 5% 0.1 W
Various manufacturers
DL1
LED Red SMT 0603
LTST-C190KRKT - Lite-on Technology Corporation
T1
NPN BJT Transistor
BC847 - Infineon
Table 47: Components for network indication application circuit
☞
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k
Ω
resistor
on the board in series to the GPIO of LENA-R8 series modules.
☞
Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (
V_INT
),
to avoid latch-up of circuits and allow a proper module boot.
☞
ESD sensitivity rating of GPIO pins is 1 kV (HBM according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting an
ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
☞
If the GPIO pins are not used, they can be left unconnected on the application board.
2.8.1.2
Guidelines for GPIO layout design
The GPIO pins are generally not critical for layout.