u-blox LEA-M8S, Hardware Integration Manual

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LEA-M8S / LEA-M8T - Hardware Integration Manual
UBX-13003140 - R07 Production Information Hardware description
Page 6 of 31
USB bus powered is not supported.
Figure 2: USB Interface
Name Component Function Comments
U1 LDO Regulates VBUS (4.4 …5.25 V)
down to a voltage of 3.3 V. Almost no current requirement (~1 mA)
C23,
C24 Capacitors Required according to the specification of LDO U1
D2 Protection
diodes Protect circuit from overvoltage
/ ESD when connecting. Use low capacitance ESD protection such as ST Microelectronics USBLC6-2.
R4, R5 Serial
termination
resistors
Establish a full-speed driver
impedance of 28…44
Ω
A value of 27
Ω
is recommended.
R11 Resistor 100 k
Ω
is recommended for USB self-powered setup. For bus-powered setup,
R11 can be ignored.
Table 1: Summary of USB external components
1.4.3 Display Data Channel (DDC)
An I
2
C compatible Display Data Channel (DDC) interface is available for serial communication with an external
host CPU. The interface only supports operation in slave mode (master mode is not supported). The DDC
protocol and electrical interface are fully compatible with the Fast-Mode of the I
2
C industry standard. DDC pins
SDA
and
SCL
have internal pull-up resistors.
For more information about the DDC implementation, see the u-blox M8 Receiver Description Including Protocol
Specification [3]. For bandwidth information, see the LEA-M8S Data Sheet [1]
.
For timing parameters, consult the
I2C-bus specification [8].
The u-blox M8 DDC interface supports serial communication with u-blox cellular modules. See the
specification of the applicable cellular module to confirm compatibility.
1.4.4 SPI (LEA-M8T ONLY)
An SPI interface is available for communication to a host CPU with LEA-M8T module.
SPI is not available in the default configuration, because its pins are shared with the UART and DDC
interfaces. The SPI interface can be enabled by connecting D_SEL to ground. For speed and clock
frequency, see the
NEO/LEA-M8T Data Sheet [2]
1.4.5 TX Ready signal
The TX Ready signal indicates that the receiver has data to transmit. A listener can wait on the TX Ready signal
instead of polling the DDC or SPI interfaces. The UBX-CFG-PRT message lets you configure the polarity and the
number of bytes in the buffer before the TX Ready signal goes active. The TX Ready signal can be mapped to
UART TXD (PIO 06). The TX Ready function is disabled by default.
The TX-ready functionality can be enabled and configured by AT commands sent to the involved u-blox
cellular module supporting the feature. For more information, see the
GPS Implementation and Aiding
Features in u-blox wireless modules [9].