EVK-NORA-B1 - User guide
UBX-20030319 - R05
Hardware description
Page 14 of 32
C1-Public
2.10
External SEGGER J-Link™ debug interface
External target hardware can be connected to J10 for firmware programming and debug. The
SEGGER debug interface is implemented, as shown in Figure 10.
J3 is implemented with a 2x5, 10-pin header on 1.27 mm centers.
Figure 10: External J-Link debug interface
To enable the external J-Link connection, ensure the following are implemented on the target
hardware:
•
EXT_VTG
is used by the debug interface as an input to sense power applied to the external circuit.
Only voltages of 3.0 V to 3.3 V are supported. Target hardware operating voltages outside of this
range require the use of an external SEGGER J-Link Debug Probe. Connect
EXT_VTG
to the
NORA-B1 series power supply (
VDD
) on the target hardware.
•
Connect
GND
to
GND
on the target hardware.
•
Connect
EXT_SWDIO
to
SWDIO
and
EXT_SWCLK
to
SWDCLK
on the target NORA-B1 module.
•
(Optional) Connect
EXT_SWO
and/or
nEXT_RESET
on the target NORA-B1 module.
•
Connect external power to the target hardware, and then connect the EVK-NORA-B1 to USB.
☞
At this point, the debug interface interacts with the target hardware instead of the on-board
NORA-B1 module. LED7 illuminates to indicate activity at the Debug Out connector.
☞
Only Nordic Semiconductor nRF5 devices are supported, including u-blox ANNA-B1, BMD-3,
NINA-B1, NINA-B3, NINA-B4, and NORA-B1 series modules.
☞
Rev C EVK hardware cannot use the Debug Out connector to program another Rev C EVK through
its Debug In port. However, the Debug Out port can be used to program any other supported target
hardware. Other programmers, like the J-Link Base, can be used to program Rev C EVK hardware
through its Debug In port. Rev D / Rev E hardware is not restricted.
