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3.5.1 CPU Common Options Submenu
Platform First Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts
from each bank.
Enabled
/ Disabled / Auto
Core Performance Boost
Disable CPB
Disabled /
Auto
Global C-state Control
Controls IO based C-state generation and DF C-states.
Disabled
/
Enabled
/ Auto
SEV-ES ASID Space Limit Control
SEV-ES ASID Space Limit Control parameters
Manual
/ Auto
Local APIC Mode
Local APIC Mode
xAPIC
/
x2APIC
/ Auto
Summary of Contents for S8253
Page 12: ...http www tyan com 12 2 2 Block Diagram S8253 Block Diagram...
Page 13: ...http www tyan com 13 2 3 Motherboard Mechanical Drawing...
Page 65: ...http www tyan com 65 3 3 7 2 CPU1 Information...
Page 80: ...http www tyan com 80 3 3 15 NVMe Configuration...
Page 81: ...http www tyan com 81 3 3 16 SATA Configuration...
Page 92: ...http www tyan com 92...
Page 93: ...http www tyan com 93...
Page 97: ...http www tyan com 97 3 4 1 1 Socket 0 Information...
Page 98: ...http www tyan com 98 3 4 1 2 Socket 1 Information...
Page 99: ...http www tyan com 99 3 5 AMD CBS Menu...
Page 103: ...http www tyan com 103 3 5 2 DF Common Options Submenu...
Page 107: ...http www tyan com 107 3 5 3 UMC Common Options Submenu...
Page 108: ...http www tyan com 108 3 5 3 1 DDR4 Common Options Submenu...
Page 117: ...http www tyan com 117 3 5 7 FCH Common Options Submenu...
Page 122: ...http www tyan com 122 3 6 2 BMC Network Configuration Submenu...
Page 147: ...http www tyan com 147 BIOS Temp Sensor Name Explanation...
Page 150: ...http www tyan com 150 NOTE...