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3.5.1 CPU Common Options
CCD/Core/Thread Enablement
CCD/Core/Thread Enablement.
Prefetcher Settings
Prefetcher Settings.
Platform First Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupts
from each bank.
Enabled / Disabled /
Auto
Core Performance Boost
Disable CPB.
Disabled /
Auto
Global C-state Control
Controls IO based C-state generation and DF C-states.
Disabled / Enabled /
Auto
Summary of Contents for S8030
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Page 13: ...http www tyan com 13 2 2 Block Diagram S8030 Block Diagram...
Page 14: ...http www tyan com 14 2 3 Mainboard Mechanical Drawing...
Page 31: ...http www tyan com 31...
Page 40: ...http www tyan com 40 NOTE...
Page 53: ...http www tyan com 53 3 3 2 2 1 Add an Attempt...
Page 76: ...http www tyan com 76 3 3 12 1 CPU 0 Information Read only...
Page 77: ...http www tyan com 77 3 3 13 SATA Configuration Read only...
Page 78: ...http www tyan com 78 3 3 14 NVMe Configuration Read only...
Page 86: ...http www tyan com 86 3 4 1 1 Socket 0 Information Read only...
Page 108: ...http www tyan com 108 3 5 5 FCH Common Options AC Power Loss Options AC Power Loss Options...
Page 138: ...http www tyan com 138 BIOS Temp Sensor Name Explanation...
Page 143: ...http www tyan com 143 4 The installation of the M 2 latch is now complete...
Page 144: ...http www tyan com 144 NOTE...