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PCle Gen3 RxCtLEp setting
The range of the setting is (0~15) This setting has to be specified basing on
platform design and following the guideline.
3.7.1.2 DIMM Information Submenu
DIMM profile
Select DIMM timing profile that should be used.
[Default DIMM profile] / [Custom Profile] / [XMP Profile1] / [XMP Profile2]
Default is [Default DIMM profile]
Memory Frequency Limiter
Maximum Memory Frequency Selections in Mhz
[Auto] / [1067] / [1333] / [1600] / [1867] / [2133] / [2400] /[2667]
Default is [Auto]
ECC Support
Enable or disable DDR ECC support
[Enabled] / [Disabled]
Summary of Contents for S5510
Page 13: ...http www TYAN com 13 2 1 Board Image S5510GM3NR ...
Page 15: ...http www TYAN com 15 2 2 Block Diagram S5510GM3NR Block Diagram ...
Page 16: ...http www TYAN com 16 S5510G2NR BTO Block Diagram ...
Page 17: ...http www TYAN com 17 S5510G2NR LE Block Diagram ...
Page 18: ...http www TYAN com 18 S5510G2NR HE BTO Block Diagram ...
Page 21: ...http www TYAN com 21 Jumper Placement J42 J43 J44 J45 J9 J10 J35 J33 J46 ...
Page 23: ...http www TYAN com 23 J2 J1 J8 J23 J24 J20 J25 SW1 ID_LED ...
Page 26: ...http www TYAN com 26 J27 J28 J34 J26 JP3 JP4 ...
Page 28: ...http www TYAN com 28 J41 J40 J39 J38 J37 J36 ...
Page 64: ...http www TYAN com 64 ...
Page 65: ...http www TYAN com 65 3 6 9 Super I O Configuration Super IO Chip Read Only ...
Page 89: ...http www TYAN com 89 3 11 Event Logs ...
Page 100: ...http www TYAN com 100 NOTE ...