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Appendix II: BIOS POST Code
Code
Beeps / Description
Code
Beeps / Description
02h Verify Real Mode
3Ah Autosize cache
03h Disable Non-Maskable Interrupt (NMI) 3Ch Advanced configuration of chipset registers
04h Get CPU type
3Dh
Load alternate registers with CMOS values
06h Initialize system hardware
42h
Initialize interrupt vectors
08h Initialize chipset with initial POST
values
45h POST
device
initialization
09h Set IN POST flag
46h
2-1-2-3. Check ROM copyright notice
0Ah Initialize CPU registers
48h
Check video configuration against CMOS
0Bh Enable CPU cache
49h
Initialize PCI bus and devices
0Ch Initialize caches to initial POST values 4Ah Initialize all video adapters in system
0Eh Initialize I/O component
4Bh QuietBoot start (optional)
0Fh Initialize the local bus IDE
4Ch
Shadow video BIOS ROM
10h Initialize Power Management
4Eh Display BIOS copyright notice
11h Load alternate registers with initial
POST values
50h
Display CPU type and speed
12h Restore CPU control word during
warm boot
51h
Initialize EISA board
13h Initialize PCI Bus Mastering devices
52h
Test keyboard
14h Initialize keyboard controller
54h
Set key click if enabled
16h 1-2-2-3. BIOS ROM checksum
58h
2-2-3-1. Test for unexpected interrupts
17h Initialize
cache
before
memory
autosize
59h
Initialize POST display service
18h 8254
timer
initialization
5Ah Display prompt "Press F2 to enter SETUP"
1Ah 8237 DMA controller initialization
5Bh Disable CPU cache
1Ch Reset
Programmable
Interrupt
Controller
5Ch
Test RAM between 512 and 640 KB
20h 1-3-1-1. Test DRAM refresh
60h
Test extended memory
22h 1-3-1-3. Test 8742 KBD Controller
62h
Test extended memory address lines
24h Set ES segment register to 4 GB
64h
Jump to UserPatch1
26h Enable A20 line
66h
Configure advanced cache registers
28h Autosize DRAM
67h
Initialize Multi Processor APIC
29h Initialize POST Memory Manager
68h
Enable external and CPU caches
2Ah Clear 512 KB base RAM
69h
Setup System Management Mode (SMM)
area
2Ch 1-3-4-1. RAM failure on address
6Ah Display external L2 cache size
2Eh 1-3-4-3. RAM failure on data bits of
low byte of memory bus
6Bh Load custom defaults (optional)
2Fh Enable cache before system BIOS
shadow
6Ch
Display shadow-area message
30h 1-4-1-1. RAM failure on data bits of
high byte of memory bus
6Eh Display possible high address for UMB
recovery
32h Test CPU bus-clock frequency
70h
Display error messages
33h Initialize Phoenix Dispatch Manager
72h
Check for configuration errors
36h Warm start shut down
76h
Check for keyboard errors
38h Shadow system BIOS ROM
7Ch Set up hardware interrupt vectors
