Linear Regulator Control and supervisory Sections
Component references are to sheet 2 of the circuit diagram unless stated. Note that 0V and the
returns for the +5V and -5V auxiliary supplies for this circuitry are effectively at the
positive
output terminal potential of the power supply.
Voltage Control Amplifiers
- When the output is switched on CMOS analogue selector IC7-A
applies the voltage programme voltage at PJ1-19 to the input of noninverting buffer amplifier IC5-
C and amplifier input current is removed via R74,IC7-C in non-programmable versions. Presets
VR3,VR2 remove control loop offset and trim programme gain respectively. The buffered output
is applied to the differential input voltage error amplifier around IC5-A. Preset VR1 is adjusted for
maximum output-sense voltage rejection. Capacitors C41,C42 minimise noise and are matched.
R70,R71,C36,C46 assist loop stability. D23-26 and feedback clamp D40,R77,R78 limit IC5-A
input and output excursions and speed amplifier recovery. IC5-A controls the output via D11.
Current Control Amplifier -
The current limit programme voltage at PJ1-20 is attenuated by
VR6,R81,R79,R208. When output is switched on CMOS analogue selector IC7-B applies
attenuated programme voltage from R79/R208 to the non- inverting input of current error amplifier
IC5-D. The voltage across the sense terminals of the four terminal output current sense resistor
R54 is applied to IC5-D inverting input via R87,R115. At current limit IC5-D takes over output
control via D12. Presets VR8 and VR6,VR9 remove control loop offset and trim maximum
indicated and output current respectively. Network R56,R84,R88 compensates for output sink
current removed via R80.
Output Off Control -
Output on-off control is entirely electronic and exercised by OPCTL from
the front panel output switch (or CPU board in programmable versions) via debounce C35,R26.
When output is switched off OPON goes low so that CMOS analogue selector IC7-A applies a
low negative voltage from R72,R73 to IC5-C input setting the supply output to about -200mV
while selector IC7-B applies a low positive voltage from R82,R83 to IC5-D input setting the
output current limit to about 50mA.
Constant Voltage/Current Status Detection
- Transistor detector circuits Q25,R148,R149,R152
and Q26,R150,R151,R153 detect whether the output of the voltage or current error amplifier is
controlling the output of the power supply and provide corresponding digital outputs from PJ1-29
and PJ1-30 to the metering/CPU boards.
Over Voltage Detection -
The output of attenuating differential amplifier IC5- B is proportional to
the output sense voltage. When this exceeds the OVP programme voltage applied to PJ1-18
amplifier IC6-A output goes high. During shut down OVP detection is inhibited via D32.
Supervisory Fault Latch -
IC9-B,IC8-D, IC12-D form a master fault latch which can be tripped
(set), driving IC9-B low and disabling switchmode and linear regulators via IC9-A, by a variety of
faults detected by the surrounding circuitry:
(i)
Activation of over voltage (OVP) detector/comparator IC5-B/IC6-A for about 200 usecs
(C70,R139,IC12-A).
(ii)
Opening of thermostat TS2/TS3 on 35V/10A or 18V/20A respectively, on overheating of
secondary side heatsink SK2/SK3 via IC8-B.
(iii)
If no switchmode output pulses are detected by pulse detector R45,C37,Q27,D60 for
about 20 secs (C69,R140,IC8-B) due to TS1 opening on primary side heatsink
overtemperature.
(iv)
Transistors detectors Q16,R202,R203 or Q17,R204,R205 turning on due to excessive
load-sense terminal podential differences for about 350 usecs (C71,R147,IC9-B) on
miswiring of load or sense terminals.
The TRIPPED output at PJ1-28 goes high on tripping of the fault latch. The fault latch is reset at
switch on via LED1,R27 or while reset line CPU RUN is driven low in programmable versions.
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