MITSUBISHI ELECTRIC MOTHERBOARD DIVISION
PAGE 19 OF 47
SMbus controller (motherboard management)
Real-time clock
ACPI power management logic
Packaged in a 324 pin BGA
The two IDE interfaces are completely independent and can operate concurrently. Both can also
be configured as a PCI bus master.
The major busses (processor, memory, PCI and AGP) all operate independently to achieve a
high degree of concurrency. Most CPU-DRAM and AGP-DRAM transfers can occur
concurrently with PCI transfers and so consume no PCI bus bandwidth.
The second level cache is contained within the processor module. There is no provision for a
third level cache. Cache size is determined by the type of CPU fitted, refer to your CPU
manufacturer for this information.
!
There are two DIMM sockets on the motherboards that accept 168-pin un-buffered SDRAM
modules to the Intel PC SDRAM un-buffered memory module specification. PC100 modules are
required when using processors with a 100MHz bus. Either PC66 or PC100 modules may be
used with 66MHz bus processors. All modules must support SPD (serial presence detect) to
allow the BIOS to determine the memory configuration and set up the chipset optimally. These
modules contain a small EEPROM that describes the module capabilities in detail - including
speed, capacity and organisation. EDO modules are not supported.
64-bit modules.
2 or 4 bank organisation
Asymmetric or symmetric memory addressing.
Single or double-sided modules.
!%
The BIOS is contained in a flash ROM device soldered directly to the motherboard and includes
the code listed below. The motherboard will automatically perform a BIOS recovery operation if
it detects a valid recovery disk during the boot sequence. An override jumper that prevents all
writes (recovery or update) provides update protection. The BIOS ROM is accessed as a single
linear region in the memory space from 4GB-128kB (0FFFE0000 - 0FFFFFFFFh) and copied at
the top of ISA memory (0E0000 - 0FFFFFh).
Core motherboard BIOS
USB
DMI
Setup-in-ROM
Intel microcode update support and code
