1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
3
of
5
Number:
Title:
01
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA.SchDoc
Filename:
2018-05-25
Default
TEC0117
U6
SiT8008BI-73-XXS-100.000000E
CLK_X
3.3V
GND
25V
X5R
GND
U1A
GW1NR-LV9QN88C6/I5
U1B
GW1NR-LV9QN88C6/I5
U1C
G
W
1
N
R
-L
V
9
Q
N
8
8
C
6
/I
5
3.3V
3.3V
3.3V
3.3V
GND
TMS
TDI
TDO
TCK
JTAGEN
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS0
D6
D7
D8
D9
D10
D11
D12
D13
D14
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
D12_R
D11_R
CONF_DONE
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AREF
D0
D1
D2
D3
D4
D5
CLK_X
GND
GND
PIO_05
PIO_06
PIO_07
PIO_08
PIO_01
PIO_02
PIO_03
PIO_04
CLK12M
3.3V
1.2V
1.2V
25V
X5R
C15
100nF
25V
X5R
C16
100nF
25V
X5R
C18
100nF
1.2V
1.2V
1.2V
GND
GND
GND
GND
1%
R3
2K
3.3V
3.3V
6.3V
X5R
C2
4.7µF
25V
X5R
C3
100nF
25V
X5R
C4
100nF
25V
X5R
C10
100nF
GND
25V
X5R
C21
100nF
25V
X5R
C22
100nF
6.3V
X5R
C14
4.7µF
25V
X5R
C25
100nF
USER_BTN
RESET
U2
W74M64FVSSIQ
3.3V
GND
F_CS
F_CLK
F_SI
F_IO3
F_IO2
F_SO
F_CS
F_CLK
F_SI
F_IO3
F_IO2
F_SO
25V
X5R
C27
100nF
GND
3.3V
TP7
Testpoint 0.8mm