Trenz Electronic TE0712 TRM, Manual

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TE0712 TRM Revision: V14
Copyright © 2017 Trenz Electronic GmbH Page of 8 20 http://www.trenz-electronic.de
Clocking
Si5338 programmable clock generator is used to generate different clocks with 25 MHz oscillator connected
to pin IN3. The Si5338 can alternatively be clocked using pins IN1 and IN2 which are connected to B2B
connector JM3 (CLKIN2).
The Si5338 can be programmed to change the output frequency of the FPGA clocks (the Ethernet clock
must remain at 50 MHz). An I C bus is connected between the FPGA (master) and clock generator (slave).
2
Proper logic needs to be created in the FPGA to exercise the I C bus with the correct data. See the
2
reference design section for more information.
CLK Output FPGA
Bank
FPGA Pin IO Standard Net Name Default
Frequency
Notes
CLK0 34 K4/J4 DIFF_SSTL15 CLK0_P/N -- NB! Since PCB REV02.
CLK1A - - CLK50M 50 MHz PHY chip RMII reference clock.
CLK1B 34 R4 CLK50M2 -- NB! Since PCB REV02.
CLK2 216 F6/E6 Auto MGT_CLK0_P/N 125 MHz GTP transceiver clock.
CLK3 35 H4/G4 DIFF_SSTL15 PLL_CLK_P/N 50 MHz
Certain B2B connector pins are connected to the FPGA pins which are capable of handling clocking signals
from the user’s PCB (baseboard). See schematics B2B page for additional information.