Transcend HD Video Card Series Datasheet Download | Manualshive

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HD Video Card Series

4GB~16GB SDHC6 HD Video Card

Transcend Information Inc.

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Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent).

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SD_SECURITY

Describes the security algorithm supported by the card.

SD Supported Security Algorithm

Note that it is mandatory for a regular writable SD Memory Card to support Security Protocol. For ROM (Read Only) and
OTP (One Time Programmable) types of the SD Memory Card, the security feature is optional. In the case of Standard
Capacity SD Memory Card, this field shall be set to 2 (Version 1.01). In the case of High Capacity SD Memory Card, this
field shall be set to 3 (Version 2.00).

•

SD_BUS_WIDTHS

Describes all the DAT bus widths that are supported by this card.

Since SD Memory Card shall support at least the two bus modes 1bit or 4bit width then any SD Card shall set at least
bits 0 and 2 (SD_BUS_WIDTH="0101").

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Summary of Contents for HD Video Card Series

Page 1: ...e 25 85 C Durability 10 000 insertion removal cycles Compatible with SD Specification Ver 2 0 Comply with SD File System Specification Ver 2 0 Mechanical Write Protection Switch Supports Speed Class Specification up to Class 6 Supports Copy Protection for Recorded Media CPRM for SD Audio Seamless compatibility with SDMI compliant digital audio devices Form Factor 24mm x 32mm x 2 1mm Pin Definition...

Page 2: ...HD Video Card Series 4GB 16GB SDHC6 HD Video Card Transcend Information Inc 2 Architecture ...

Page 3: ... From 0v to VDD Min Current Consumption The current consumption is measured by averaging over 1 second Before first command Maximum 15 mA During initialization Maximum 100 mA Operation in Default Mode Maximum 100 mA Operation in High Speed Mode Maximum 200 mA Operation with other functions Maximum 500 mA Bus Signal Line Load The total capacitance CL the CLK line of the SD Memory Card bus is the su...

Page 4: ...lines will be consist of CHOST CBUS and one CCARD only because they are connected separately to the SD Memory Card host Host should consider total bus capacitance for each signal as the sum of CHOST CBUS and CCARD these parameters are defined by per signal The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load CL 40 pF The SD Memory Car...

Page 5: ...the requirements of the JEDEC specification JESD8 1A and JESD8 7 the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range Parameter Symbol Min Max Unit Remark Output HIGH voltage VOH 0 75 VDD V IOH 100 μA VDD min Output LOW voltage VOL 0 125 VDD V IOL 100 μA VDD min Input HIGH voltage VIH 0 625 VDD VDD 0 3 V Input LOW voltage VIL VS...

Page 6: ...CCARD 10 pF 1 card Clock frequency Identification Mode fOD 0 1 100 400 KHz CCARD 10 pF 1 card Clock low time tWL 10 ns CCARD 10 pF 1 card Clock high time tWH 10 ns CCARD 10 pF 1 card Clock rise time tTLH 10 ns CCARD 10 pF 1 card Clock fall time tTHL 10 ns CCARD 10 pF 1 card Inputs CMD DAT referenced to CLK Input set up time tISU 5 ns CCARD 10 pF 1 card Input hold time tIH 5 ns CCARD 10 pF 1 card O...

Page 7: ...ion Inc 7 Output Delay time during Data Transfer Mode tODLY 0 14 ns CL 40 pF 1 card Output Delay time during Identification Mode tODLY 0 50 ns CL 40 pF 1 card 1 0 Hz means to stop the clock The given minimum frequency range is for cases were continues clock is required ...

Page 8: ...Clock frequency Data Transfer Mode fPP 0 50 MHz CCARD 10 pF 1 card Clock low time tWL 7 ns CCARD 10 pF 1 card Clock high time tWH 7 ns CCARD 10 pF 1 card Clock rise time tTLH 3 ns CCARD 10 pF 1 card Clock fall time tTHL 3 ns CCARD 10 pF 1 card Inputs CMD DAT referenced to CLK Input set up time tISU 6 ns CCARD 10 pF 1 card Input hold time tIH 2 ns CCARD 10 pF 1 card Outputs CMD DAT referenced to CL...

Page 9: ...nd Information Inc 9 Output Delay time during Data Transfer Mode tODLY 14 ns CL 40 pF 1 card Output Hold time tOH 2 5 ns CL 40 pF 1 card Total System capacitance for each line1 CL 40 pF 1 card 1 In order to satisfy severe timing host shall drive only one card ...

Page 10: ...m or 2 5 deg Drop test 1 5m free fall UV light exposure UV 254nm 15Ws cm according to ISO 7816 1 X ray exposure 0 1 Gy of medium energy radiation 70 keV to 140 keV cumulative dose per year to both sides of the card according to ISO7816 1 Visual inspection Shape and form No warp page no mold skin complete form no cavities surface smoothness 0 1 mm cm within contour no cracks no pollution fat oil du...

Page 11: ...gister shall be implemented by the cards The 32 bit operation conditions register stores the VDD voltage profile of the card Bit 7 of OCR is newly defined for Dual Voltage Card and set to 0 in default If a Dual Voltage Card does not receive CMD8 OCR bit 7 in the response indicates 0 and the Dual Voltage Card which received CMD8 sets this bit to 1 Additionally this register includes 2 more status i...

Page 12: ...aphs MID An 8 bit binary number that identifies the card manufacturer The MID number is controlled defined and allocated to a SD Memory Card manufacturer by the SD 3C LLC This procedure is established to ensure uniqueness of the CID register OID A 2 character ASCII string that identifies the card OEM and or the card contents when used as a distribution media either on ROM or FLASH cards The OID nu...

Page 13: ...e month code 1 January The y field 19 12 is the year code 0 2000 As an example the binary value of the Date field for production date April 2001 will be 00000001 0100 CRC CRC7 checksum 7 bits 3 CSD Register Table 5 16 shows Definition of the CSD for the High Capacity SD Memory Card CSD Version 2 0 The following sections describe the CSD fields and the relevant data types for the High Capacity SD M...

Page 14: ...not explicitly defined otherwise all bit strings are interpreted as binary coded numbers starting with the left bit first CSD_STRUCTURE Field structures of the CSD register are different depend on the Physical Specification Version and Card Capacity The CSD_STRUCTURE field in the CSD register indicates its structure version The following table shows the version number of the related CSD structure ...

Page 15: ...dicates 1 ms The host should not use TAAC NSAC and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations See 4 6 2 NSAC This field is fixed to 00h NSAC should not be used to calculate time out values TRAN_SPEED The following table defines the maximum data transfer rate per one data line TRAN_SPEED ...

Page 16: ...s are supported by this card A value of 1 in a CCC bit means that the corresponding command class is supported READ_BL_LEN This field is fixed to 9h which indicates READ_BL_LEN 512 Byte READ_BL_PARTIAL This field is fixed to 0 which indicates partial block read is inhibited and only unit of block access is allowed WRITE_BLK_MISALIGN This field is fixed to 0 which indicates write access crossing ph...

Page 17: ... fixed to 7Fh which indicates 64 KBytes This value does not relate to erase operation Version 2 00 cards indicates memory boundary by AU size and this field should not be used WP_GRP_SIZE This field is fixed to 00h The High Capacity SD Memory Card does not support write protected groups WP_GRP_ENABLE This field is fixed to 0 The High Capacity SD Memory Card does not support write protected groups ...

Page 18: ...ermanently write protected TMP_WRITE_PROTECT Temporarily protects the whole card content from being overwritten or erased all write and erase commands for this card are temporarily disabled This bit can be set and reset The default value is 0 i e not write protected FILE_FORMAT This field is set to 0 Host should not use this field CRC The CRC field carries the check sum for the CSD contents The ch...

Page 19: ...ification procedure The default value of the RCA register is 0x0000 The value0x0000 is reserved to set all cards into the Stand by State with CMD7 5 DSR Register Optional The 16 bit driver stage register is described in detail in Chapter 6 5 It can be optionally used to improve the bus performance for extended operating conditions depending on parameters like bus length transfer rate or number of ...

Page 20: ... 64 bit This register shall be set in the factory by the SD Memory Card manufacturer The following table describes the SCR register content SCR_STRUCTURE Version number of the related SCR structure in the SD Memory Card Physical Layer Specification SCR Register Structure Version SD_SPEC Describes the SD Memory Card Physical Layer Specification version supported by this card SD_SPEC Physical Layer ...

Page 21: ... support Security Protocol For ROM Read Only and OTP One Time Programmable types of the SD Memory Card the security feature is optional In the case of Standard Capacity SD Memory Card this field shall be set to 2 Version 1 01 In the case of High Capacity SD Memory Card this field shall be set to 3 Version 2 00 SD_BUS_WIDTHS Describes all the DAT bus widths that are supported by this card Since SD ...

Page 22: ...HD Video Card Series 4GB 16GB SDHC6 HD Video Card Transcend Information Inc 22 Mechanical Dimension ...

Page 23: ...HD Video Card Series 4GB 16GB SDHC6 HD Video Card Transcend Information Inc 23 ...

Page 24: ...HD Video Card Series 4GB 16GB SDHC6 HD Video Card Transcend Information Inc 24 ...

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