User's Manual l TQMxE39S UM 0101 l © 2019 TQ-Group
Page 19
SMARC Connector Pin Assignment (continued)
Pin
Pin-Signal
Description
Type
Level
Remark
S53 HDA_CK / I2S2_CK
HDA: clock / I
2
S: Digital audio clock
IO
1.8 V
S54 SATA_ACT#
Active low SATA activity indicator (16 mA max)
OD
3.3 V
S55 USB5_EN_OC#
USB over-current input / enable output (both OD)
IO PU
3.3 V
OD input only
S56 ESPI_IO_2
ESPI Master Data Input / Outputs
IO
1.8 V
N/A
S57 ESPI_IO_3
ESPI Master Data Input / Outputs
IO
1.8 V
N/A
S58 ESPI_RESET#
ESPI Reset
O
1.8 V
S59 USB5+
USB differential pair
IO
USB
S60 USB5–
USB differential pair
IO
USB
S61 GND
Ground
GND
S62 US
Differential USB SuperSpeed transmit data pair
O
USB SS
S63 USB3_SSTX–
Differential USB SuperSpeed transmit data pair
O
USB SS
S64 GND
Ground
GND
S65 US
Differential USB SuperSpeed receive data pair
I
USB SS
S66 USB3_SSRX–
Differential USB SuperSpeed receive data pair
I
USB SS
S67 GND
Ground
GND
S68 USB3+
USB differential pair
IO
USB
S69 USB3–
USB differential pair
IO
USB
S70 GND
Ground
GND
S71 US
Differential USB SuperSpeed transmit data pair
O
USB SS
S72 USB2_SSTX–
Differential USB SuperSpeed transmit data pair
O
USB SS
S73 GND
Ground
GND
S74 US
Differential USB SuperSpeed receive data pair
I
USB SS
S75 USB2_SSRX–
Differential USB SuperSpeed receive data pair
I
USB SS
S76 PCIE_B_RST#
PCIe Port reset output
O
3.3 V
S77 PCIE_C_RST#
PCIe Port reset output
O
3.3 V
S78 PC
Differential PCIe Link receive data pair
I
PCIe
S79 PCIE_C_RX–
Differential PCIe Link receive data pair
I
PCIe
S80 GND
Ground
GND
S81 PC
Differential PCIe Link transmit data pair
O
PCIe
S82 PCIE_C_TX–
Differential PCIe Link transmit data pair
O
PCIe
S83 GND
Ground
GND
S84 PCIE_
Differential PCIe Link reference clock output
O
PCIe
S85 PCIE_B_REFCK–
Differential PCIe Link reference clock output
O
PCIe
S86 GND
Ground
GND
S87 PC
Differential PCIe Link receive data pair
I
PCIe
S88 PCIE_B_RX–
Differential PCIe Link receive data pair
I
PCIe
S89 GND
Ground
GND
S90 PC
Differential PCIe Link transmit data pair
O
PCIe
S91 PCIE_B_TX–
Differential PCIe Link transmit data pair
O
PCIe
S92 GND
Ground
GND
S93 DP
DP++ data differential pair
O
DP++
S94 DP0_LANE0–
DP++ data differential pair
O
DP++
S95 DP0_AUX_SEL
DP AUX select (to select between DP and HDMI)
I PD
1.8 V
PD
S96 DP
DP++ data differential pair
O
DP++
S97 DP0_LANE1–
DP++ data differential pair
O
DP++
S98 DP0_HPD
DP++ Hot Plug Detect input
I PD
1.8 V
PD
S99 DP
DP++ data differential pair
O
DP++
S100 DP0_LANE2–
DP++ data differential pair
O
DP++
S101 GND
Ground
GND
S102 DP
DP++ data differential pair
O
DP++
S103 DP0_LANE3–
DP++ data differential pair
O
DP++
S104 USB3_OTG_ID
USB OTG ID input, active high (high device)
I PU
3.3 V
4:
Configurable through TQ-flexiCFG.
