TQ TQMa8MxML, User Manual

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User's Manual l TQMa8MxML UM 0103 l © 2022, TQ-Systems GmbH Page 33
3.2.5.8 PCIe
The i.MX 8M Mini provides one PCIe 2.0 lane, the i.MX 8M Nano does not provide this feature.
The 100 MHz reference clock can be generated on the TQMa8MxML and output to PCIE_REF_CLKN/P for the PCIe card.
The 100 MHz reference clock can be generated internally and output to PCIE_REF_CLKN/P for the PCIe card.
Alternatively, the reference clock can be provided from an external source to PCIE_REF_CLKN/P.
The PCIe card must be supplied by the carrier board.
The series capacitors required by the PCIe standard must be provided on the carrier board.
i.MX 8M Mini LGA
PCIE_TXN/P
PCIE_RXN/P PCIE_TXN/P
PCIE_RXN/P
PCIE_RESREF
PCIE_REF_CLKN/P PCIE_REF_CLKN/P
GND
Figure 14: Block diagram PCIe
The following table shows the signals used by the PCIe interface.
Table 26: PCIe signals
Signal Direction CPU ball TQMa8MxML Power group
PCIE_REF_CLKN
I or O 10
A21 T17
V_1V8_ANA
PCIE_REF_CLKP B21 U17
PCIE_RXN
I
A19 R18
PCIE_RXP B19 T18
PCIE_TXN
O
A20 P19
PCIE_TXP B20 R19
Note: TQMa8MxNL, termination of PCIe interface pins
The TQMa8MxNL does not offer a PCIe interface. The i.MX 8M Nano nevertheless features the pins,
which are connected to the LGA pads of the TQMa8MxNL. Therefore, it is recommended to terminate
the signals externally when using the TQMa8MxNL.
10: Direction depends on configuration.