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User's Manual  l  TQMa7x UM 0203  l  © 2022, TQ-Systems GmbH 

 

Page  5 

 

2.2

 

Key functions and characteristics 

The following interfaces are provided by default at the TQMa7x connectors. 

1

 

 

Table 2: 

Default interfaces 

Interface 

Qty. 

Remark 

ADC 

2 

4 channels each 

CAN 

2 

FLEXCAN1 / FLEXCAN2 

CCM 

2 

1 × Differential CLK  

1 × Single-Ended CLK 

ENET / RGMII 

2 

ENET1: 10/100/1000 Base-T (Ethernet)  
ENET2: 10/100/1000 Base-T (Ethernet): only on TQMa7D 

GPIO 

9 

– 

I

2

C 

3 

I2C1 is used for devices on the TQMa7x 

JTAG 

1 

SJC / JTAG 

LCD 

1 

24 bit RGB parallel 

MIPI CSI 

1 

2 lanes 

MIPI DSI 

1 

2 lanes 

PCIe 

1 

PCIe 2.0: 1 lane; only on TQMa7D 

PWM 

4 

– 

QSPI 

1 

SPI NOR flash (assembly option) 

SAI 

1 

I

2

S / ESAI 

SDHC 

1 

uSDHC1: 4 bit, SD card UHS-I (SDR104) 

SIM 

1 

ISO-7816 smart card interface 

SPI 

2 

– 

TAMPER 

10 

– 

UART 

5 

9600 to 115200 Baud; 8N1; 4 UARTs with RTS# / CTS# 

USB HSIC 

1 

Host 

USB OTG 

2 

OTG2: Only on TQMa7D 

WDOG 

1 

WDOG output and Reset 

 
 
With an adapted pin configuration, other i.MX7 interfaces can be used alternatively to the standard configuration. 
In essence, these are: 

•

 

Parallel CSI interface 

•

 

EIM interface 

•

 

EPDC interface 

•

 

Flexible Timer Module 

•

 

General-Purpose Memory Interface 

•

 

General-Purpose Timer 

•

 

Keypad port 

•

 

Medium-Quality Sound module 

•

 

More GPIOs 

•

 

Additional SIM interface 

•

 

More Audio, I

2

C, SPI and UART interfaces 

•

 

More Watchdog Timer 

 

                                                                            

1: 

Number of interfaces and configuration depend on i.MX7 and TQMa7x derivative. 

Summary of Contents for Ma7x

Page 1: ...TQMa7x User s Manual TQMa7x UM 0203 07 01 2022 ...

Page 2: ...1 2 eFuses 11 3 2 1 3 i MX7 errata 11 3 2 1 4 Boot modes 11 3 2 1 5 Boot configuration 12 3 2 1 6 Boot interfaces 13 3 2 1 7 Boot device eMMC 13 3 2 1 8 Boot device QSPI NOR flash 14 3 2 1 9 Boot device SD card 15 3 2 2 Memory 16 3 2 2 1 DDR3L SDRAM 16 3 2 2 2 eMMC NAND flash 16 3 2 2 3 QSPI NOR flash 17 3 2 2 4 EEPROM M24C64 18 3 2 3 RTC 19 3 2 3 1 i MX7 RTC 19 3 2 3 2 RTC DS1339U 20 3 2 4 Temper...

Page 3: ...component placement 43 4 4 Adaptation to the environment 44 4 5 Protection against external effects 44 4 6 Thermal management 44 4 7 Structural requirements 44 4 8 Notes of treatment 44 5 SOFTWARE 45 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 46 6 1 EMC 46 6 2 ESD 46 6 3 Operational safety and personal security 46 6 4 Reliability and service life 46 6 5 Climate and operational conditions 47 ...

Page 4: ...e 20 ADC 23 Table 21 CCM 24 Table 22 ECSPI1and ECSPI2 24 Table 23 ENET1 and ENET2 25 Table 24 FLEXCAN 26 Table 25 GPIO 26 Table 26 I2 C signals 27 Table 27 I2 C address assignment 27 Table 28 LCD interface 28 Table 29 MIPI CSI 29 Table 30 MIPI DSI 29 Table 31 PCIe interface 29 Table 32 PWM 29 Table 33 QSPI 30 Table 34 SAI interface 30 Table 35 SIM interface 30 Table 36 JTAG modes 31 Table 37 JTAG ...

Page 5: ...39U RTC on TQMa7x 20 Figure 10 Block diagram temperature sensor interface SE97BTP 21 Figure 11 Block diagram ADC 23 Figure 12 Block diagram SD card interface 34 Figure 13 Block diagram Watchdog 35 Figure 14 Block diagram Reset 35 Figure 15 Block diagram TQMa7x power supply 36 Figure 16 Block diagram Supervisor VCC5V 38 Figure 17 Block diagram 3 3 V supply on carrier board 38 Figure 18 Block diagra...

Page 6: ...4 2 3 2 5 4 1 6 6 Typo formatting external links updated IMX7DCEC Data Sheet added Warning extended Updated Added Removed Updated 0202 24 10 2018 Petz All 3 2 5 4 3 2 7 4 3 2 5 9 3 2 7 6 Table 60 Formatting links updated Power domain added Information added Warnings updated Package temperature replaced with Case temperature Case temperature DDR3L SDRAM changed to 95 C 0203 07 01 2022 Kreuzer All C...

Page 7: ......

Page 8: ...d trademarks are rightly protected by a third party 1 3 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality Nor does TQ Systems GmbH assume guarantee for further usage of the information Liability claims against TQ Systems GmbH referring to material or non material related damages caused due to usage or non usag...

Page 9: ...s important details or aspects for working with TQ products Command A font with fixed width is used to denote commands file names or menu items 1 7 Handling and ESD tips General handling of your TQ products The TQ product may only be used and serviced by certified personnel who have taken note of the information the safety regulations in this document and all related rules and regulations A genera...

Page 10: ...cations of the components used for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These documents are stored at TQ Systems GmbH Chip errata It is the user s responsibility to make sure all errata published by the manufacturer of each component are taken note of The manufacturer s advice...

Page 11: ...d offers an outstanding computing performance A suitable i MX7 derivative i MX7Solo i MX7Dual can be selected for each requirement All essential i MX7 pins are routed to the TQMa7x connectors There are therefore no restrictions using the TQMa7x with respect to an integrated customised design All essential components like i MX7 DDR3L SDRAM eMMC and power management are already integrated on the TQM...

Page 12: ...ly on TQMa7D PWM 4 QSPI 1 SPI NOR flash assembly option SAI 1 I2 S ESAI SDHC 1 uSDHC1 4 bit SD card UHS I SDR104 SIM 1 ISO 7816 smart card interface SPI 2 TAMPER 10 UART 5 9600 to 115200 Baud 8N1 4 UARTs with RTS CTS USB HSIC 1 Host USB OTG 2 OTG2 Only on TQMa7D WDOG 1 WDOG output and Reset With an adapted pin configuration other i MX7 interfaces can be used alternatively to the standard configura...

Page 13: ... and simplifies the selection and configuration i MX Pins Tool NXP Tool The electrical and pin characteristics are to be taken from the i MX7 Data Sheets 1 2 the i MX7 Reference Manuals 5 6 and the PMIC Data Sheet 4 Attention TQMa7x malfunction or destruction Depending on the configuration many i MX7 pins can provide several different functions Please take note of the information in the i MX7 Refe...

Page 14: ...GND 57 58 UART3_RTS UART 3 3 V I M5 L1 I 3 3 V UART UART5_RX 59 60 UART3_RX UART 3 3 V I M1 L2 O 3 3 V UART UART5_TX 61 62 UART3_TX UART 3 3 V O M2 P 0 V Power DGND 63 64 DGND Power 0 V P Pout 1 8 V Power VDDA1P8_SW2 65 66 VCC1V8_IN Power 1 8 V Pin P 0 V Power DGND 67 68 DGND Power 0 V P AC1 A 1 8 V ADC ADC2_IN0 69 70 ADC1_IN0 ADC 1 8 V A AD1 AC2 A 1 8 V ADC ADC2_IN1 71 72 ADC1_IN1 ADC 1 8 V A AD3...

Page 15: ...II RGMII1_TD0 53 54 DGND Power 0 V P E17 O 3 3 V RGMII RGMII1_TD1 55 56 RGMII1_RD0 RGMII 3 3 V I E14 E18 O 3 3 V RGMII RGMII1_TD2 57 58 RGMII1_RD1 RGMII 3 3 V I F14 D18 O 3 3 V RGMII RGMII1_TD3 59 60 RGMII1_RD2 RGMII 3 3 V I D13 E16 O 3 3 V RGMII RGMII1_TX_CTL 61 62 RGMII1_RD3 RGMII 3 3 V I E13 P 0 V Power DGND 63 64 RGMII1_RX_CTL RGMII 3 3 V I E15 F6 I O 3 3 V SIM SIM_TRXD 65 66 DGND Power 0 V P ...

Page 16: ...A19 O 1 8 V MIPI DSI_CLK_N 35 36 DGND Power 0 V P B19 O 1 8 V MIPI DSI_CLK_P 37 38 CSI_D0_N MIPI 1 8 V I A16 P 0 V Power DGND 39 40 CSI_D0_P MIPI 1 8 V I B16 A20 O 1 8 V MIPI DSI_D0_N 41 42 DGND Power 0 V P B20 O 1 8 V MIPI DSI_D0_P 43 44 TEMP_EVENT Config 2 O P 0 V Power DGND 45 46 RFU D3 I 3 3 V GPIO GPIO5_IO09 47 48 RFU C3 I 3 3 V GPIO GPIO5_IO10 49 50 RFU P 0 V Power DGND 51 52 DGND Power 0 V ...

Page 17: ...8 V MIPI DSI_CLK_N 35 36 DGND Power 0 V P B19 O 1 8 V MIPI DSI_CLK_P 37 38 CSI_D0_N MIPI 1 8 V I A16 P 0 V Power DGND 39 40 CSI_D0_P MIPI 1 8 V I B16 A20 O 1 8 V MIPI DSI_D0_N 41 42 DGND Power 0 V P B20 O 1 8 V MIPI DSI_D0_P 43 44 TEMP_EVENT Config 2 O P 0 V Power DGND 45 46 RFU D3 I O 3 3 V ENET ENET2_MDIO 47 48 RFU C3 O 3 3 V ENET ENET2_MDC 49 50 RFU P 0 V Power DGND 51 52 DGND Power 0 V P H25 O...

Page 18: ...ntion Malfunction or destruction Please take note of the current i MX7 errata 7 3 2 1 4 Boot modes The i MX7 contains a ROM with integrated boot loader After power up the boot code initializes the hardware and then loads the program image from the selected boot device As standard boot device of the TQMa7x e g the integrated e MMC or the optional SPI NOR Flash can be chosen As an alternative to boo...

Page 19: ...ept It is recommended to provide a redundant update concept for field software updates when designing a carrier board 3 2 1 5 Boot configuration Some general settings are done with eFuses independent from the boot device Table 9 General boot settings i MX7 TQMa7x eFuse Option Setting 3 Signal Pin BOOT_CFG19 Infinite Loop for debug purposes 0 Disabled 1 Enabled 0 LCD_DATA19 X2 104 BOOT_CFG18 i MX7 ...

Page 20: ...ATA13 X2 96 BOOT_CFG12 0 LCD_DATA12 X2 93 BOOT_CFG11 Port Selection 00 uSDHC1 01 uSDHC2 10 uSDHC3 1 LCD_DATA11 X2 94 BOOT_CFG10 0 LCD_DATA10 X2 91 BOOT_CFG9 eMMC Reset 0 Disabled 1 Enabled 0 LCD_DATA09 X2 92 BOOT_CFG7 Boot Speed 0 Normal Regular Boot 1 Fast Boot 0 LCD_DATA07 X2 88 BOOT_CFG6 Bus width 000 1 bit 001 4 bit 010 8 bit 101 4 bit DDR MMC 4 4 110 8 bit DDR MMC 4 4 0 LCD_DATA06 X2 85 BOOT_...

Page 21: ...0 QSPI0 1 Reserved 0 LCD_DATA11 X2 94 BOOT_CFG10 SDR SMP 000 Default 001 111 Reserved 0 LCD_DATA10 X2 91 BOOT_CFG9 0 LCD_DATA09 X2 92 BOOT_CFG8 0 LCD_DATA08 X2 89 BOOT_CFG7 Half Speed Phase Selection 0 At non inverted clock 1 At inverted clock 0 LCD_DATA07 X2 88 BOOT_CFG6 Half Speed Delay 0 One clock delay 1 Two clock delay 0 LCD_DATA06 X2 85 BOOT_CFG5 Full Speed Phase Selection 0 At non inverted ...

Page 22: ..._DATA10 X2 91 BOOT_CFG9 SD Power Cycle 0 Disabled 1 Enabled 0 LCD_DATA09 X2 92 BOOT_CFG8 SD Loopback Clock Source 0 Through SD pad 1 Direct 0 LCD_DATA08 X2 89 BOOT_CFG7 Boot Speed 0 Normal Regular Boot 1 Fast Boot 0 LCD_DATA07 X2 88 BOOT_CFG4 Bus Width 0 1 bit 1 4 bit 1 LCD_DATA04 X2 83 BOOT_CFG3 Speed Selection 000 Normal SDR12 001 High SDR25 010 Not applicable for uSDHC1 7 011 Not applicable for...

Page 23: ...M 1 0 DRAM_SDCLK0 P N DRAM_ODT 1 0 DRAM_CS 1 0 RAS CAS SDWE SDCKE 1 0 SDBA 2 0 DRAM_DATA 15 0 DDR3L SDRAM 2 DRAM_DQM 3 2 DRAM_SDQS 1 0 P N DRAM_SDQS 3 2 P N DRAM_RESET Figure 3 Block diagram DDR3L SDRAM interface 3 2 2 2 eMMC NAND flash An 8 Gbyte SanDisk SDINBDG4 8G T eMMC or an 8 Gbyte Micron MTFC8GAKAJCN 1M eMMC is assembled on the TQMa7x The eMMC contains the boot loader and can contain operat...

Page 24: ...eMMC mode 1 bit 4 bit 8 bit Fast boot Remark Normal Speed Yes Yes Yes No 8 Not tested High Speed Yes Yes Yes No 8 HS200 n a 9 Yes Yes No 8 HS400 n a 9 n a 9 Yes No 8 Default in BSP provided by TQ Systems Attention Malfunction or destruction An implementation of the SET_DSR routine from the BSP Rev 0104 must no longer be carried out for modules from REV 0200 onwards as this can lead to malfunctions...

Page 25: ...ck diagram external QSPI NOR flash interface Attention Malfunction or destruction The QSPI interface may only be used as memory interface Other SPI devices have to be connected at the eCSPI interfaces 3 2 2 4 EEPROM M24C64 The TQMa7x provides a 64 Kbit serial EEPROM type STM M24C64 RDW6TP which contains TQMa7x specific data see Table 16 The user can also store own data in this EEPROM It is connect...

Page 26: ...e characteristics of the quartz used The type FC 135R assembled on the TQMa7x has a standard frequency tolerance of 20 ppm 25 C Parabolic coefficient max 0 04 10 6 C2 Coin Cell Li Coin Cell SuperCap typ 3 V Connector TQMa7x PMIC i MX7x LICELL LICELL VSNVS SNVS VCC5V 5 V VIN 4 2 V Figure 8 Block diagram i MX7 RTC supply The RTC power domain SNVS of the i MX7 is supplied by the PMIC internal regulat...

Page 27: ...pe CM7V used on the TQMa7x has a standard frequency tolerance of 20 ppm 25 C Parabolic coefficient max 0 04 10 6 C2 Connector TQMa7x PMIC i MX7 LICELL DS1339U VCC V33 I2C I2C1 VBACKUP VCC5V 5 V 4 2 V VIN Coin Cell Li Coin Cell SuperCap typ 3 V Figure 9 Block diagram DS1339U RTC on TQMa7x The I2 C address of the RTC is 0x68 110 1000b The following table shows the current consumption of the DS1339U ...

Page 28: ... 3 6 V The following block diagram shows how the temperature sensor is connected to the i MX7 i MX7 Temp sensor I2C1_SCL I2C1_SDA SCL SDA Connector TEMP_EVENT EVENT Figure 10 Block diagram temperature sensor interface SE97BTP Half of the memory area of 256 bytes can be permanently protected against write accesses by register accesses Thus module internal data can be deposited here which are to be ...

Page 29: ...Qty Chapter Remark ADC 2 3 2 5 2 4 channels each CAN 2 3 2 5 6 FLEXCAN1 FLEXCAN2 CCM 2 3 2 5 3 1 CLK differential In Out 1 CLK Single Ended In ECSPI 2 3 2 5 4 ECSPI1 ECSPI2 ENET 1 3 2 5 5 RGMII GbE ENET 1 3 2 5 5 RGMII GbE only TQMa7D GPIO 9 3 2 5 7 I2 C 3 3 2 5 8 I2C1 I2C2 I2C3 LCD 1 3 2 5 9 24 bit RGB MIPI_CSI 1 3 2 5 10 MIPI_DSI 1 3 2 5 11 PCIe 1 3 2 5 12 Only TQMa7D PWM 4 3 2 5 13 QSPI 1 3 2 5...

Page 30: ...igh precision VCC1V8_IN X1 66 can be connected with VCC1V8_OUT on the carrier board For high precision an external voltage reference can be connected to VCC1V8_IN This is however application specific but has to meet at least the following parameters Voltage at VCC1V8_IN 1 71 V to 1 89 V typically 1 8 V Current rating VCC1V8_IN max 15 mA Adherence of i MX7 Power Sequencing The ADC as well as the i ...

Page 31: ...O X1 52 CCM_CLK2 I X1 55 3 2 5 4 ECSPI The i MX7 provides four ECSPI interfaces ECSPI1 and ECSPI2 are available as primary function at the TQMa7x connectors The following table shows the signals used by the ECSPI1 and the ECSPI2 interfaces Table 22 ECSPI1and ECSPI2 Signal Direction Pin Remark Power domain ECSPI1_MISO I X1 34 VCC3V3_V33 ECSPI1_MOSI O X1 32 ECSPI1_SCLK O X1 46 ECSPI1_SS0 O X1 36 ECS...

Page 32: ...1_RD0 I X2 56 RGMII1_RD1 I RGMII1_RD1 I X2 58 RGMII1_RD2 I RGMII1_RD2 I X2 60 RGMII1_RD3 I RGMII1_RD3 I X2 62 RGMII1_RX_CTL I RGMII1_RX_CTL I X2 64 RGMII1_RXC I RGMII1_RXC I X2 52 RGMII1_TD0 O RGMII1_TD0 O X2 53 RGMII1_TD1 O RGMII1_TD1 O X2 55 RGMII1_TD2 O RGMII1_TD2 O X2 57 RGMII1_TD3 O RGMII1_TD3 O X2 59 RGMII1_TX_CTL O RGMII1_TX_CTL O X2 61 RGMII1_TXC O RGMII1_TXC O X2 49 ENET2_MDIO I O GPIO5_I...

Page 33: ...terface function most i MX7 pins can also be configured as GPIO All these GPIOs can trigger an interrupt Details are to be taken from the i MX7 Reference Manuals 5 6 and the i MX7 Data Sheets 1 2 In addition several pins are already marked as GPIO and are available on the TQMa7x connectors The following table shows the GPIO signals provided Table 25 GPIO Signal Pin Power domain GPIO1_IO09 X1 80 VC...

Page 34: ...I2C3_SCL O X1 39 I2C3_SDA I O X1 37 The following table shows the I2 C devices connected to the I2C1 bus on the TQMa7x Table 27 I2 C address assignment Component Address Remark EEPROM M24C64 0x50 101 0000b Temperature sensor SE97BTP 0x1E 001 1110b Temperature register EEPROM SE97BTP 0x56 101 0110b Normal Mode RWP 0x36 011 0110b Protected Mode PWP RTC DS1339U 0x68 110 1000b Assembly option PMIC PF3...

Page 35: ...ATA01 O X2 82 LCD_DATA00 O X2 79 LCD_HSYNC O X2 76 LCD_VSYNC O X2 78 LCD_CLK O X2 72 LCD_ENABLE O X2 68 LCD_RESET O X2 75 Display signals LCD_DATA 19 0 also serve as BOOT_CFG 19 0 signals to load the boot configuration It has to be ensured that displays connected to the carrier board do not interfere with the boot configuration loaded at these pins Alternatively the Serial Downloader or the intern...

Page 36: ...I_D1_P O X3 31 DSI_D1_N O X3 29 DSI_D0_P O X3 43 DSI_D0_N O X3 41 3 2 5 12 PCIe The i MX7D provides a PCIe interface which is routed to the TQMa7x connectors These pins are NC at the TQMa7S The following table shows the signals used by the PCIe interface Table 31 PCIe interface Signal Direction Pin Remark Power domain PCIE_TX_N O X3 70 Only available with TQMa7D NC with TQMa7S VDDA_PHY_1P8 i MX7 i...

Page 37: ...5 15 SAI To connect an audio codec via e g I2S the signals of the SAI1 are available from the three SAI interfaces on the TQMa7x connectors The following table shows the used signals of the SAI interface Table 34 SAI interface Signal Direction 11 Pin Power domain SAI1_MCLK O X2 39 VCC3V3_V33 SAI1_RX_DATA I X2 38 SAI1_RX_BCLK I X2 40 SAI1_RX_SYNC I X2 42 SAI1_TX_DATA O X2 30 SAI1_TX_BCLK O X2 32 SA...

Page 38: ...9 i MX7 internal 47 kΩ PU JTAG_TDO O X1 91 i MX7 internal 100 kΩ PU JTAG_TRST I X1 85 i MX7 internal 47 kΩ PU JTAG_MOD I X1 93 4 7 kΩ PD on TQMa7x i MX7 internal 100 kΩ PU 3 2 5 18 TAMPER The i MX7 provides protection against unauthorised opening or manipulation of a device by tamper detection Ten TAMPER pins are available for this purpose at the TQMa7x connectors The following table shows the ava...

Page 39: ...gnal Direction Pin Remark Power domain UART3_RX I X1 60 VCC3V3_V33 UART3_TX O X1 62 UART3_CTS O X1 56 UART3_RTS I X1 58 UART4_RX I X3 14 UART4_TX O X3 16 UART4_CTS O X3 10 UART4_RTS I X3 12 UART5_RX I X1 59 UART5_TX O X1 61 UART6_RX I X1 111 RS 232 on MBa7x VCC3V3_VLDO4 UART6_TX O X1 113 RS 232 on MBa7x UART6_CTS O X1 115 RS 232 on MBa7x UART6_RTS I X1 117 RS 232 on MBa7x UART7_RX I X1 112 UART7_T...

Page 40: ...SB_OTG1_OC I X2 17 USB_OTG1_VBUS P X2 21 Connect to 5 V on carrier board n a The following table shows the signals used by the USB OTG2 interface Table 41 USB OTG2 Signal Direction Pin Remark Power domain USB_OTG2_DP I O X3 22 Only on TQMa7D NC on TQMA7S VCC3V3_V33 USB_OTG2_DN I O X3 20 Only on TQMa7D NC on TQMA7S USB_OTG2_ID I X3 13 Only on TQMa7D NC on TQMA7S Device Mode Connect with Micro USB c...

Page 41: ...is used during card detection for this purpose The signal is available as an output at the TQMa7x connectors PMIC_SD_VSEL is not required on the carrier board for the SD card function and should therefore be not connected The IO voltage must be switched by software as defined in the SD card specification It is not permitted to switch the voltage by feeding a voltage at pin PMIC_SD_VSEL The followi...

Page 42: ...G33 VCC WDOG1 RESET_IN MR RESET 3 3 V Figure 13 Block diagram Watchdog 3 2 6 Reset Reset inputs or outputs are available at the TQMa7x connectors The following block diagram shows the reset signals wiring i MX7 Connector IMX7_POR NP 3 3 V PF3000 RESETBMCU Open Drain RESET_IN RESET_OUT POR_B Internal 100 kΩ PU Figure 14 Block diagram Reset The following table describes the reset signals available a...

Page 43: ...PMIC DC DC converter 5 V 4 2 V Figure 15 Block diagram TQMa7x power supply The characteristics and functions of the pins and signals are to be taken from the PMIC Data Sheet 4 and the i MX7 Data Sheets 1 2 3 2 7 2 Other TQMa7x supply inputs In addition to VCC5V two more supply inputs are provided by the TQMa7x Table 46 TQMa7x Supply inputs Voltage Pin Usage VIN IIN VCC1V8_IN X1 66 Supplies i MX7 r...

Page 44: ...ctional instabilities of the TQMa7x 3 2 7 4 TQMa7x power consumption The given power consumption has to be seen as an approximate value The TQMa7x power consumption strongly depends on the application the mode of operation and the operating system The following table shows power supply and TQMa7x power consumption parameters Table 48 Parameter TQMa7x power consumption 5 V TQMa7x Mode Current consu...

Page 45: ...ltage monitoring does not detect overvoltage Do not try to reprogram the PMIC since this may cause the i MX7 or other peripherals on the TQMa7x to operate outside their specification An excessively high input voltage can lead to malfunction deterioration or destruction of the TQMa7x 3 2 7 6 Power Up sequence TQMa7x carrier board The TQMa7x meets the sequencing required by the i MX7 1 2 through the...

Page 46: ...C3V3_MB_EN Note BOOT_MODE BOOT CFG The BOOT_MODE and BOOT CFG pins each have dedicated reference voltages which are provided by the TQMa7x see 3 2 9 3 3 2 7 7 Standby The i MX7 supports in combination with the PMIC several Standby modes Details can be found in the i MX7 Data Sheets 1 2 and the PMIC Data Sheet 4 Note Suspend to RAM Suspend to RAM is not supported in LPSR mode TQMa7x with discrete R...

Page 47: ...C and Power Management are provided at the TQMa7x connectors Table 49 PMIC Signal Direction Pin Remark Power domain PMIC_PWRON I X1 21 Switches the PMIC off when signal is active Power cycle starts when signal is deactivated Low active signal To deactivate Float or pull up to 3 3 V VSNVS 3 0 V IMX_ONOFF I X1 24 Switches i MX7 to Off or SNVS mode Depends on software and current i MX7 Power Mode See...

Page 48: ...XL is strongly recommended See chapter 4 9 for further information Attention Component placement on the carrier board 2 5 mm should be kept free on the carrier board on both long sides of the TQMa7x for the extraction tool MOZI8XXL The following table shows suitable mating plug connectors for the carrier board Table 51 Suitable carrier board mating connectors Manufacturer Part number Remark Stack ...

Page 49: ... s Manual l TQMa7x UM 0203 l 2022 TQ Systems GmbH Page 42 4 2 TQMa7x dimensions Figure 19 TQMa7x dimensions side view Figure 20 TQMa7x dimensions top view Figure 21 TQMa7x dimensions top view through TQMa7x ...

Page 50: ... 02xx 120 119 120 119 80 79 2 1 2 1 2 1 AK3 Figure 23 TQMa7x component placement bottom revision 02xx The labels on the TQMa7x show the following information Table 52 Labels on TQMa7x revision 02xx Label Content AK1 First MAC address plus one additional reserved consecutive MAC address tests performed AK2 TQMa7x version and revision AK3 Serial number ...

Page 51: ... heat sink weight and mounting position depending on the specific mode of operation e g dependence on clock frequency stack height airflow and software Particularly the tolerance chain PCB thickness board warpage BGA balls BGA package thermal pad heatsink as well as the maximum pressure on the i MX7 must be taken into consideration when connecting the heat sink see 8 The i MX7 is not necessarily t...

Page 52: ...for the combination of TQMa7x and MBa7x The boot loader U Boot provides module specific as well as board specific settings e g i MX7 configuration PMIC configuration SDRAM configuration and timing eMMC configuration Pin multiplexing Clocks Pin configuration Driver strengths These settings have to be adapted for other bootloaders More information can be found in the TQMa7x Support Wiki 11 ...

Page 53: ...ccording to DIN EN 55022 2010 Limit Value Class A 6 2 ESD In order to avoid interspersion on the signal path from the input to the protection circuit in the system the protection against electrostatic discharge should be arranged directly at the inputs of a system As these measures always have to be implemented on the carrier board no special preventive measures are taken on the TQMa7x Following m...

Page 54: ...or destruction TQMa7x heat dissipation The TQMa7x belongs to a performance category in which a cooling system is essential It is the user s sole responsibility to define a suitable heat sink weight and mounting position depending on the specific mode of operation e g dependence on clock frequency stack height airflow and software Particularly the tolerance chain PCB thickness board warpage BGA bal...

Page 55: ...duct embedded PC applies 7 5 Battery No batteries are assembled on the TQMa7x 7 6 Packaging The TQMa7x is delivered in reusable packaging 7 7 Other entries By environmentally friendly processes production equipment and products we contribute to the protection of our environment To be able to reuse the TQMa7x it is produced in such a way a modular construction that it can be easily repaired and dis...

Page 56: ...ace Module EMC Electromagnetic Compatibility eMMC embedded Multimedia Card Flash EN Europäische Norm European standard ENET Ethernet ESAI Enhanced Serial Audio Interface ESD Electrostatic Discharge EuP Energy using Products FR 4 Flame Retardant 4 GPIO General Purpose Input Output HRCW Hard Reset Configuration Word HSIC High Speed Inter Chip I O Input Output I2C Inter Integrated Circuit I2S Integra...

Page 57: ...ndependent Interface RoHS Restriction of the use of certain Hazardous Substances ROM Read Only Memory RS 232 Recommended Standard serial interface RTC Real Time Clock RWP Reversible Write Protected SAI Serial Audio Interface SD card Secure Digital Card SD eSD SDXC Secure Digital enhanced Secure Digital SD eXtended Capacity SD MMC Secure Digital Multimedia Card SDHC Secure Digital Host Controller S...

Page 58: ...ct Lifetime Usage AN5334 1 0 05 2017 NXP 4 Power Management integrated circuit for i MX7 i MX 6SL SX UL PF3000 PMIC 9 0 08 2017 NXP 5 i MX 7Dual Applications Processor Reference Manual IMX7DRM 1 0 01 2018 NXP 6 i MX 7Solo Applications Processor Reference Manual IMX7SRM 0 1 08 2016 NXP 7 i MX7S i MX7D IMX7D_2N09P Mask Set Errata 1 0 08 2017 NXP 8 i MX 7DS Power Consumption Measurements AN5383 1 0 0...

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Page 60: ...TQ Systems GmbH Mühlstraße 2 l Gut Delling l 82229 Seefeld Info TQ Group l TQ Group ...

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