User's Manual l TQMa6x & TQMa6xP UM 0403 l © 2019, TQ-Systems GmbH
Page 23
3.2.5.11
IPU
The i.MX6 provides two parallel display interfaces (maximum resolution: 4096 × 2048). One of them, DISP0, is routed to the
connectors as primary function. Information with respect to the supported types of displays and formats are to be taken
from the NXP Reference Manuals (4), (5), and (6).
The following table shows the signals used by the display interface DISP0.
Table 30:
Signals DISP0
Signal name
Direction
i.MX6 ball
TQMa6x
Remark
DISP0_DAT23
O
W24
X2–158
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA23
DISP0_DAT22
O
V24
X2–157
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA22
DISP0_DAT21
O
T20
X2–156
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA21
DISP0_DAT20
O
U22
X2–155
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA20
DISP0_DAT19
O
U23
X2–154
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA19
DISP0_DAT18
O
V25
X2–153
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA18
DISP0_DAT17
O
U24
X2–152
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA17
DISP0_DAT16
O
T21
X2–151
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA16
DISP0_DAT15
O
T22
X2–150
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA15
DISP0_DAT14
O
U25
X2–149
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA14
DISP0_DAT13
O
R20
X2–148
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA13
DISP0_DAT12
O
T24
X2–147
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA12
DISP0_DAT11
O
T23
X2–144
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA11
DISP0_DAT10
O
R21
X2–143
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA10
DISP0_DAT9
O
T25
X2–142
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA9
DISP0_DAT8
O
R22
X2–141
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA8
DISP0_DAT7
O
R24
X2–140
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA7
DISP0_DAT6
O
R23
X2–139
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA6
DISP0_DAT5
O
R25
X2–138
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA5
DISP0_DAT4
O
P20
X2–137
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA4
DISP0_DAT3
O
P21
X2–136
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA3
DISP0_DAT2
O
P23
X2–135
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA2
DISP0_DAT1
O
P22
X2–134
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA1
DISP0_DAT0
O
P24
X2–133
Display Output RGB-Data i.MX6 signal: IPU1_DISP0_DATA0
DISP0_HSYNC
O
N25
X2–128
Display Output Horizontal Sync i.MX6 signal: IPU1_DI0_PIN2
DISP0_VSYNC
O
N20
X2–130
Display Output Vertical Sync i.MX6 signal: IPU1_DI0_PIN3
DISP0_CLK
O
N19
X2–125
Display Output Clock i.MX6 signal: IPU1_DI0_DISP_CLK
DISP0_DRDY
O
N21
X2–127
Display Output Data Enable i.MX6 signal: IPU1_DI0_PIN15
DISP0_CONTRAST
O
P25
X2–129
Display Backlight PWM i.MX6 signal: IPU1_DI0_PIN4
14:
Currently not supported; use PWM1 instead.
