User's Manual l MBLX2160A UM 0101 l © 2022, TQ-Systems GmbH
Page 18
Clock generation (continued)
Two programmable clock drivers are provided on the MBLX2160A for the clock structure.
Figure 7:
Clock distribution on the MBLX2160A
Both clock drivers are connected to the LX2160A via I2C1.
A reference clock of 125 MHz is required for the RGMII Ethernet interfaces on EC1 and EC2.
On the TQMLX2160A the clock signal is differentially routed to an LVDS receiver.
MBLX2160A
TQMLX2160A
Module
Connector
LVDS
Receiver
LX
CPU
3.3 V
1.8 V
LVDS
V
CM
= 1.2 V
GTX_CLK125
Clock
Driver
Figure 8:
LVDS receiver
LVDS is terminated with 100 Ω on the TQMLX2160A.
2 pcs Fractional PLL available:
- 1 x 156.25 MHz
- 1 x 100 MHz with Spread Spectrum
Possible without spread spectrum
integer
