User's Manual l MBLX2160A UM 0101 l © 2022, TQ-Systems GmbH
Page 17
3.3
Clock generation
SYSCLK and DDRCLK are generated on the TQMLX2160A. Therefore the following clocks must be applied externally:
•
SerDes clocks
•
ECx Ethernet clocks
The clocks depend on the chosen SerDes protocol, see following table:
Table 9:
Valid SerDes RCW Encodings and Reference Clocks
SerDes protocol (given lane)
Valid Reference Clock
Frequency
Valid setting
as determined by
SRDS_PRTCL_S
n
Valid setting
as determined by
SRDS_PLL_REF_CLK_SEL_S
n
Valid setting
as determined by
SRDS_DIV_*_S
n
High Speed Serial Interfaces
PCI Express (2.5 Gbps)
(doesn’t negotiate upwards)
100 MHz
Any PCIe
0: 100 MHz
11: 2.5 Gbps
125 MHz
1: 125 MHz
PCI Express (5 Gbps)
(can negotiate up to 5 Gbps)
100 MHz
Any PCIe
0: 100 MHz
10: 5 Gbps
125 MHz
1: 125 MHz
PCI Express (8 Gbps)
(can negotiate up to 8 Gbps)
100 MHz
Any PCIe
0: 100 MHz
01: 8 Gbps
125 MHz
1: 125 MHz
PCI Express (16 Gbps)
(can negotiate up to 16 Gbps)
100 MHz
Any PCIe
0: 100 MHz
00: 16 Gbps
125 MHz
1: 125 MHz
SATA (1.5, 3 or 6 Gbps)
100 MHz
Any SATA
0: 100 MHz
Don’t care
125 MHz
1: 125 MHz
Networking interfaces
SGMII (1.25 Gbps)
100 MHz
SGMII @ 1.25 Gbps
0: 100 MHz
Don’t care
125 MHz
1: 125 MHz
USXGMII/XFI, 40 GE
(each lane: 10.3125 Gbaud)
156.25 MHz
USXGMII/XFI, 40 GE @
10.3125 Gbaud
0: 156.25 MHz
Don’t care
161.1328125 MHz
1: 161.1328125 MHz
25 GE, 50 GE, 100 GE
(each lane: 25.78125 Gbaud)
161.1328125 MHz
25 GE, 50 GE, 100 GE @
25.78125 Gbaud
0: 161.1328125 MHz
Don’t care
The MBLX2160A is designed for the configuration 0b00:
•
For 1.25, 2.5, 3, 5, 6, 8 or 16 GHz protocols: 100 MHz
•
For 3.125 or 6.25 GHz protocols:
125 MHz
•
For 10.3125 GHz protocols:
156.25 MHz
•
For 25.78125 GHz protocols:
161.1328125 MHz
The following SerDes clocks are used:
•
PCIe
100 MHz (for requirements according to Gen 3)
•
SGMII
100 MHz
•
SATA
100 MHz
•
XFI
156.25 MHz
•
CAUI-4
161.1328125 MHz
•
RGMII ECx_GTX_CLK125
125 MHz
