Toshiba TMP91C824F, Data Book

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TMP91C824
91C824-84
(1) Master Enable bits
Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the master bit
which is used to enable or disable settings for the corresponding address area. Writing “1” to this bit
enables the settings. Reset disables (sets to “0”)<B0E>, <B1E> and <B3E>, and enabled (sets to
“1”) <B2E>. This enables area CS2 only.
(2) Data bus width selection
Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip select/wait control
register specifies the width of the data bus. This bit should be set to “0” when memory is to be
accessed using a 16-bit data bus and to “1” when an 8-bit data bus is to be used.
This process of changing the data bus width according to the address being accessed is known as
“dynamic bus sizing”. For details of this bus operation see Table 3.6.2.
Table 3.6.2 Dynamic bus sizing
CPU Data
Operand Data
Bus Width
Operand Start
Address
Memory Data
Bus Width
CPU Address
D15 to D8 D7 to D0
8 bits 2n + 0 xxxxx b7 ~ b0 2n + 0
(Even number)
16 bits 2n + 0 xxxxx b7 ~ b0
8 bits 2n + 1 xxxxx b7 ~ b0
8 bits
2n + 1
(Odd number)
16 bits 2n + 1 b7 ~ b0 xxxxx
2n + 0 xxxxx b7 ~ b0 8 bits
2n + 1 xxxxx b15 ~ b8
2n + 0
(Even number)
16 bits 2n + 0 b15 ~ b8 b7 ~ b0
2n + 1 xxxxx b7 ~ b0 8 bits
2n
+
2 xxxxx b15 ~ b8
2n + 1 b7 ~ b0 xxxxx
16 bits
2n + 1
(Odd number)
16 bits
2n
+
2 xxxxx b15 ~ b8
2n + 0 xxxxx b7 ~ b0
2n + 1 xxxxx b15 ~ b8
2n + 2 xxxxx b23 ~ b16
8 bits
2n + 3 xxxxx b31 ~ b24
2n + 0 b15 ~ b8 b7
−
b0
2n + 0
(Even number)
16 bits
2n
+
2 b31 ~ b24 b23
−
b16
2n + 1 xxxxx b7 ~ b0
2n + 2 xxxxx b15 ~ b8
2n + 3 xxxxx b23 ~ b16
8 bits
2n + 4 xxxxx b31 ~ b24
2n + 1 b7 ~ b0 xxxxx
2n + 2 b23 ~ b16 b15 ~ b8
32 bits
2n + 1
(Odd number)
16 bits
2n + 4 xxxxx b31 ~ b24
(note): “xxxxx” indicates that the input data from these bits are ignored during a read. During a write, indicates
that the bus for these bits goes too high-impedance; also, that the write strobe signal for the bus remains inactive.