Toshiba TMP91C824F Data Book Download Page 53

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TMP91C824

91C824-50

(6) Attention

point

The instruction execution unit and the bus interface unit of this CPU operate independently.

Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears

the corresponding interrupt request flag, the CPU may execute the instruction that clears the

interrupt request flag(*1) between accepting and reading the interrupt vector. In this case, the CPU

reads the default vector 0008H and reads the interrupt vector address FFFF08H.

To avoid the avobe plogram, place instructions that clear interrupt request flags after a DI

instruction.

In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POP SR

instruction, disable an interrupt by DI instruction before execution of POP SR instruction.

In addition, take care as the following 2 circuits are exceptional and demand special attention.

In Level Mode INT0 is not an edge-triggered interrupt. Hence, in Level

Mode the interrupt request flip-flop for INT0 does not function. The

peripheral interrupt request passes through the S input of the flip-flop and

becomes the Q output. If the interrupt input mode is changed from Edge

Mode to Level Mode, the interrupt request flag is cleared automatically.

INT0 Level Mode

If the CPU enters the interrupt response sequence as a result of INT0 going

from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence

has been completed. If INT0 is set to Level Mode so as to release a Halt state,

INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the Halt

state is released. (Hence, it is necessary to ensure that input noise is not

interpreted as a 0, causing INT0 to revert to 0 before the Halt state has been

released.)

When the mode changes from Level Mode to Edge Mode, interrupt request

flags which were set in Level Mode will not be cleared. Interrupt request

flags must be cleared using the following sequence.

LD (IIMC), 00H; Switches interrupt input mode from Level Mode to

Edge Mode.

LD (INTCLR), 0AH; Clears interrupt request flag.

INTRX

The interrupt request flip-flop can only be cleared by a Reset or by reading

the Serial Channel Receive Buffer. It cannot be cleared by an instruction.

(note): The following instructions or pin input state changes are equivalent to instructions that clear the

interrupt request flag.

INT0: Instructions which switch to Level Mode after an interrupt request has been

generated in Edge Mode.

The pin input change from High to Low after interrupt request has been generated

in Level Mode. (H

→

INTRX: Instruction which read the Receive Buffer

Summary of Contents for TMP91C824F

Page 1: ...REV2 6 July 12 2002 Rev 2 6 12 July 2002 16bit Micro controller TLCS 900 L1 series TMP91C824F Data Book ...

Page 2: ...91C824 56 3 5 3 Port 5 91C824 58 3 5 4 Port 6 91C824 61 3 5 5 Port 7 91C824 62 3 5 6 Port 8 91C824 66 3 5 7 Port B 91C824 67 3 5 8 Port C 91C824 70 3 5 9 Port D 91C824 73 3 6 Chip Select Wait Controller 91C824 78 3 7 8 bit Timers TMRA 91C824 88 3 8 Memory Management Unit 91C824 108 3 9 Serial Channel 91C824 119 3 10Serial Bus Interface 91C824 151 3 11 Analog Digital Converter 91C824 179 3 12 Watch...

Page 3: ...824 Modify the frequency of Micro DMA Change the reference 2 Add the comment about package Mistake 16 240 Modify the input frequency of DFMCR1 Mistake 29 Modify the name SBI0BR1à SBI0BR0 in the table 3 3 2 Mistake 30 251 Add the limitation about HALT mode Mistake Important matter 48 236 Add the comment to the register IIMC bit6 Mistake 55 Modify the comment in the figure Mistake 87 Add the figure ...

Page 4: ...ecification as defined by Philips For a discussion of how the reliability of microcontrollers can be predicted please refer to Section 1 3 of the chapter entitled Quality and Reliability Assurance Handling Precautions TOSHIBA is continually working to improve the quality and the reliability of its products Nevertheless semiconductor devices in general can malfunction or fail due to their inherent ...

Page 5: ...illegal instruction 23 internal interrupts 7 priority levels are selectable 5 external interrupts 7 priority levels are selectable among 4 interrupts are selectable edge mode 15 Input output ports 35 pins External 16 bit data bus memory 16 Stand by function Three Halt modes Idle2 programmable Idle1 and Stop 17 Triple clock controller Clock doubler DFM circuit is inside Clock gear function Select a...

Page 6: ... RESET AM0 AM1 WDT Watch DogTimer Clock Gear Clock Doubler SIO UART SIO1 RD WR HWR P52 WAIT P53 BUSRQ P54 BUSAK P55 R W P56 L OSC EMU0 EMU1 PORT 5 CS WAIT CONTROLLER 4 BLOCK PORT 2 CS0 toCS3 CS2A CS2E INTERRUPT CONTROLLER INT0 to INT3 MELODY ALARM OUT MLDALM PD7 8BIT TIMER TMRA1 TA1OUT PB1 8BIT TIMER TMRA2 8BIT TIMER TMRA3 TA3OUT PB2 Initial Function After Reset B C D E H L ADTRG P83 SCLK1 CTS1 PC...

Page 7: ...P72 SI SCL TA0IN PB0 TA1OUT PB1 TA3OUT PB2 INT0 PB3 INT1 PB4 INT2 PB5 INT3 PB6 P55 BUSAK DVCC1 A11 A12 A13 A14 A15 P20 A16 P21 A17 P22 A18 P23 A19 P24 A20 P25 A21 DVCC2 NMI DVSS2 P26 A22 P27 A23 P17 D15 P16 D14 P15 D13 P14 D12 P13 D11 P12 D10 P11 D9 P10 D8 D7 D6 D5 D4 D3 D2 D1 D0 PD7 MLDALM PD6 ALARM MLDALM PD5 SCOUT SCLK1 CTS1 PC5 RXD1 PC4 TXD1 PC3 SCLK0 CTS0 PC2 RXD0 PC1 TXD0 PC0 EMU1 EMU0 XT2 X...

Page 8: ...72 2050 118 48 D4 1504 2050 82 A4 918 2045 15 PB0 2050 251 49 D5 1630 2050 83 A3 778 2045 16 PB1 2050 384 50 D6 1757 2050 84 A2 639 2045 17 PB2 2050 517 51 D7 2045 1750 85 A1 499 2045 18 PB3 2050 650 52 P10 2045 1614 86 A0 359 2045 19 PB4 2050 783 53 P11 2045 1478 87 RD 219 2045 20 PB5 2050 916 54 P12 2045 1341 88 WR 80 2045 21 PB6 2050 1049 55 P13 2045 1205 89 PZ2 59 2045 22 P54 2050 1182 56 P14 ...

Page 9: ... O Output Port 55 I O port with pull up resistor Bus Acknowledge signal used to acknowledge Bus Release P56 WAIT 1 I O Input Port 56 I O port with pull up resistor Wait pin used to request CPU bus wait P60 CS0 1 Output Output Port 60 Output port Chip select 0 Outputs 0 when address is within specified address area P61 CS1 1 Output Output Port 61 Output port Chip Select 1 outputs 0 when address is ...

Page 10: ...to 87 port Pin used to input ports Analog input 0 to 7 Pin used to Input to A D conveter A D trigger Signal used to request A D start with used to P83 PB0 TA0IN 1 I O Input Port B0 I O port 8bit timer 0 input Timer 0 input PB1 TA1OUT 1 I O Output Port B1 I O port 8bit timer 1 output Timer 0 input or Timer 1 output PB2 TA3OUT 1 I O Output Port B2 I O port 8bit timer 3 output Timer 2 input or Timer ...

Page 11: ...rm output pin PD7 MLDALM 1 Output Output Port D7 Output port Melody Alarm output pin NMI 1 Input Non Maskable Interrupt Request Pin interrupt request pin with programmable falling edge level or with both edge levels programmable AM0 to 1 2 Input Operation mode Fixed to AM1 0 AM0 1 16 bit external bus or 8 16 bit dynamic sizing Fixed to AM1 0 AM0 0 8 bit external bus fixed EMU0 1 Output Open pin EM...

Page 12: ... the reset is accept the CPU Sets as follows the program counter PC in accordance with the reset vector stored at address FFFF00H to FFFF02H PC 0 to 7 value at FFFF00H address PC 15 to 8 value at FFFF01H address PC 23 to 16 value at FFFF02H address Sets the stack pointer XSP to 100H Sets bits IFF2 0 of the status register SR to 111 sets the interrupt level mask register to level 7 Sets the MAX bit...

Page 13: ...23 0 DATA IN D0 15 D0 15 sampling After reset released startting 2 wait read cycle Note Pull up internal High z DATA OUT sampling P52 input mode RESET RD WR HWR CS0 1 3 0FFFF00H CS2 DATA IN XT1 XT2 Figure 3 1 1 TMP91C824 Reset Timing Chart ...

Page 14: ...rea R R R R R8 16 R d8 16 nnn Direct area n 64Kbyte area nn Internal I O 4KByte Internal RAM 8K Byte 003000H 010000H Internal area FFFF00H FFFFFFH Vector table 256 Byte External memory 000100H 000FE0H Figure 3 2 1 Memory Map Note Address 000FE0H 00FFFH is assigned for the TOSHIBA reserve area user can t use ...

Page 15: ... 3 stand by controller and 4 noise reduction circuit It is used for low power low noise systems This chapter is organized as follows 3 3 1 Block diagram of system clock 3 3 2 SFRs 3 3 3 System clock controller 3 3 4 Prescaler clock controller 3 3 5 Clock doubler DFM 3 3 6 Noise reducing circuit 3 3 7 Stand by controller ...

Page 16: ... mode Operate only oscillator c Triple clock mode trasision Figure instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction interrupt instruction instruction interrupt interrupt instruction instruction instruction interrupt NOTE NOTE It s prohibited to control DFM in SLOW mode when shifting from SLOW mode to NOR...

Page 17: ...ator Lock up timer DFM SYSCR0 WUEF SYSCR2 WUPTM1 WUPTM 0 DFMCR0 ACT1 ACT 0 DLUPTM X1 X2 Clock Doubler DFM fDFM fOSCH 4 2 16 4 fc 16 fc 8 fc 4 fc 2 fc DFMCR0 ACT1 ACT 0 SYSCR1 GEAR2 GEAR 0 2 4 fc 16 fFPH fSYS 2 fSYS CPU RAM ADC Interrupt controller WDT I O ports prescaler φT0 SIO0 to1 SBI RTC φT fs φT0 fs φT SYSCR0 XEN RXTEN High Frequency oscillator 8 prescaler prescaler MLD ALM Figure 3 3 2 Block...

Page 18: ...4 3 2 1 0 bit Symbol SYSCK GEAR2 GEAR1 GEAR0 Read Write R W After reset 0 1 0 0 Function Select system clock 0 fc 1 fs Select gear value of high frequency fc 000 fc 001 fc 2 010 fc 4 011 fc 8 100 fc 16 101 reserved 110 reserved 111 reserved 7 6 5 4 3 2 1 0 bit Symbol SCOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE Read Write R W R W R W R W R W R W R W After reset 0 1 0 1 1 0 0 Function 0 fs 1 fSYS...

Page 19: ...0 10 write 1BH Limitation point on the use of DFM 1 It s prohibited to execute DFM enable disable control in the SLOW mode fs write to DFMCR0 ACT1 0 10 You should control DFM in the NORMAL mode 2 If you stop DFM operation during using DFM DFMCR0 ACT1 0 10 you shouldn t execute that change the clock fDFM to fOSCH and stop the DFM at the same time Therefore the above executions should be separated i...

Page 20: ... to following 1 st KEY 2 nd KEY 1 st KEY EMCCR1 5AH EMCCR2 A5H in succession write 2 nd KEY EMCCR1 A5H EMCCR2 5AH in succession write bit Symbol ENFROM ENDROM ENPROM FFLAG DFLAG PFLAG Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 CS1A write Operation flag CS2B 2G write operation Flag CS2A write Operation Flag Function CS1A area detect control 0 disable 1 enable CS2B 2G area detect con...

Page 21: ...fSYS is set to 0 5 MHz when the 16 MHz oscillator is connected to the X1 and X2 pins 1 Switching from Normal Mode to Slow Mode When the resonator is connected to the X1 and X2 pins or to the XT1 and XT2 pins the warm up timer can be used to change the operation frequency after stable oscillation has been attained The warm up time can be selected using SYSCR2 WUPTM0 WUPTM1 This warm up timer can be...

Page 22: ...s warm up timer WUP BIT 2 SYSCR0 JR NZ WUP Detects stopping of warm up timer SET 3 SYSCR1 Changes fSYS from fc to fs RES 7 SYSCR0 Disables high frequency oscillation note x means don t care means no change fc fs Counts up by fs XEN X1 X2 pins XT1 XT2 pins XTEN Warming Up Timer End of Warming Up Timer SYSCK System Clock fSYS Enables low Frequency Clears and starts warming up timer End of warming up...

Page 23: ...rts warm up timer WUP BIT 2 SYSCR0 JR NZ WUP Detects stopping of warm up timer RES 3 SYSCR1 Changes fSYS from fs to fc RES 6 SYSCR0 Disables low frequency oscillation note x means don t care means no change Counts up by fc XEN X1 X2 pins XT1 XT2 pins XTEN Warming Up Timer End of Warming Up Timer SYSCK System Clock fSYS Enables High Frequency Clears and Starts Warming Up Timer End of warming up tim...

Page 24: ...er writing the register value There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing To execute the instruction next to the clock gear switching instruction by the clock gear after changing input the dummy instruction as follows instruction to execute the write cycle Example SYSCR1 EQU 00E1H LD SYSCR1 XXXX0001B Change...

Page 25: ...his circuit requires time to stabilize This is called the lock up time The following example shows how DFM is used DFMCR0 EQU 00E8H DFMCR1 EQU 00E9H LD DFMCR1 00001011B DFM parameter setting LD DFMCR0 01X0XXXXB Set lock up time to 212 4 MHz Enables DFM operation and starts lock up LUP BIT 5 DFMCR0 JR NZ LUP Detects end of lock up LD DFMCR0 10X0XXXXB Changes fc from 4 MHz to 16 MHz X Don t care 10 ...

Page 26: ...rt up Warming up start WUP BIT 2 SYSCR0 JR NZ WUP LD SYSCR1 0 B Change the system clock fs to fOSCH LD DFMCR0 01 0 B DFM start up lock up start LUP BIT 5 DFMCR0 JR NZ LUP LD DFMCR0 10 0 B Change the system clock fOSCH to fDFM OK Low frequency oscillator operation mode fs high frequency oscillator Operate High frequency oscillator operation mode fOSCH DFM start up DFM use mode fDFM LD SYSCR1 0 B Ch...

Page 27: ... stop LD SYSCR1 1 B Change the system clock fDFM to fS LD DFMCR0 11 B Change the internal clock fC fDFM to fOSCH LD DFMCR0 00 B DFM stop LD SYSCR0 0 B High frequency oscillator stop OK DFM use mode fDFM Set the STOP mode High frequency oscillator operation mode fOSCH DFM stop HALT High frequency oscillator stop LD SYSCR2 01 B Set the STOP mode This command can execute before use of DFM LD DFMCR0 1...

Page 28: ...ROM protection of register contents 1 Reduced drivability for high frequency oscillator Purpose Reduces noise and power for oscillator when a resonator is used Block diagram resonator C2 C1 Enable oscillation X1 pin EMCCR0 DRVOSCH fOSCH STOP EMCCR0 EXTIN X2 pin Setting method The drivability of the oscillator is reduced by writing 0 to EMCCR0 DRVOSCH register By reset DRVOSCH is initialized to 1 a...

Page 29: ...0 to the EMCCR0 DRVOSCL register By Reset DRVOSCL is initialized to 1 3 Single drive for high frequency oscillator Purpose Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used Block diagram X1 pin X2 pin Enable oscillation STOP EMCCR0 EXTIN EMCCR0 DRVOSCH fOSCH Setting method The oscillator is disabled and starts operation as buffer by ...

Page 30: ... B0CS B1CS B2CS B3CS BEXCS MSAR0 MSAR1 MSAR2 MSAR3 MAMR0 MAMR1 MAMR2 MAMR3 2 MMU LOCAL0 1 2 3 3 Clock gear SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR3 4 DFM DFMCR0 DFMCR1 Operation explanation Execute and release of protection write operation to specified SFR become possible by setting up a double key to EMCCR1 and EMCCR2 register Double key 1st KEY Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd ...

Page 31: ...e kinds of ROM is fixed as for Flash ROM Option Program ROM Data ROM Program ROM are as follows on the logical address memory map 1 Flash ROM Address 400000H 7FFFFFH 2 Data ROM Address 800000H BFFFFFH 3 Program ROM Address C00000H FFFFFFH For these address admission prohibition of detection of write operation sets it up with EMCCR3 ENFROM ENDROM ENPROM And INTP1 interruption occurred within which ...

Page 32: ...2 SFR seting operation during IDLE2 mode Internal I O SFR TMRA01 TA01RUN I2TA01 TMRA23 TA23RUN I2TA23 SIO0 SC0MOD1 I2S0 SIO1 SC1MOD1 I2S1 A D converter ADMOD1 I2AD WDT WDMOD I2WDT SBI SBI0BR0 I2SBI0 Idle1 Only the oscillator and the RTC real time clock continue to operate ƒ Stop All internal circuits stop operating The operation of each of the different Halt Modes is described in Table 3 3 3 Table...

Page 33: ... interrupt mask register releasing the the halt mode is executed In this case interrupt processing and CPU starts executing the instruction next to the HALT instruction but the interrupt request flag is held at 1 Note Usually interrupts can release all halts status However the interrupts NMI INT0 3 INTKEY INTRTC INTALM0 to 4 which can release the HALT mode may not be able to do so if they are inpu...

Page 34: ... the halt mode The priority level interrupt request level of non maskable interrupts is fixed to 7 the highest priority level There is not this combination type 1 Releasing the halt mode is executed after passing the warmming up time Note 1 When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status hold level H until starting interrupt processing If level ...

Page 35: ... Mode only the internal oscillator and the RTC MLD continue to operate The system clock in the MCU stops The pin status in the IDLE1 mode is depended on setting the register SYSCR2 SELDRV DRVE Table 3 3 6 summarizes the state of these pins in the IDLE mode1 In the Halt state the interrupt request is sampled asynchronously with the system clock however clearance of the Halt state i e restart of ope...

Page 36: ...her Normal Mode or Slow Mode can be selected using the SYSCR0 RSYSCK register Therefore RSYSCK RXEN and RXTEN must be set See the sample warm up times in Table 3 3 5 Figure 3 3 8 illustrates the timing for clearance of the Stop Mode Halt state by an interrupt Interrupt for release Warming up time STOP mode N e x t N e x t 2 X1 A0 23 RD WR D0 15 Data Data Figure 3 3 8 Timing chart for Stop Mode Hal...

Page 37: ...ncy after released no change 9005H HALT NMI 9006H LD XX XX RETI Clears and starts hit warm up timer high frequency end NMI Interrupt Routine Note When different modes are used before and after STOP mode as the above mentioned there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of HALT instruction during...

Page 38: ...e Output mode Input Input Output P80 P87 Input pin PB0 PB2 PC0 PC5 Input mode Output mode Input Output PB3 PB6 Input mode Output mode Input Input Output NMI Input pin Input Input RESET Input Input Input AM0 AM1 Input Input Input IDLE1 Input Input X1 XT1 Input STOP IDLE1 Output Output X2 XT2 Output STOP H Level output XT2 is Hi Z H Level output XT2 is Hi Z Input for input mode input pin is invalid ...

Page 39: ... CPU interrupt mask register IFF 2 0 If the priority level of the interrupt is higher than the value of the interrupt mask register the CPU accepts the interrupt The interrupt mask register IFF 2 0 value can be updated using the value of the EI instruction EI num sets IFF 2 0 data to num For example specifying EI 3 enables the maskable interrupts which priority level set in the interrupt controlle...

Page 40: ...unt Count 1 Count 0 No Yes Data transfer by micro DMA No Micro DMA processing RETI instruction POP SR POP PC INTNEST INTNEST 1 Clear vector register generating micro DMA trasfer and interrupt INTTC0 3 Clear interrupt requenst flag Interrupt vector value V read Interrupt request F F clear Micro DMA soft start request Presupposes that one of four channels of micro DMA start vector register is set to...

Page 41: ...ETI restores the contents of Program Counter PC and Status Register SR from the stack and decreases the Interrupt Nesting counter INTNEST by 1 1 Non maskable interrupts cannot be disabled by a user program Maskable interrupts however can be enabled or disabled by a user program A program can set the priority level for each interrupt source A priority level setting of 0 or 7 will disable an interru...

Page 42: ...3CH 0FH 17 INTALM2 ALM2 64Hz 0040H FFFF40H 10H 18 INTALM3 ALM3 2Hz 0044H FFFF44H 11H 19 INTALM4 ALM4 1Hz 0048H FFFF48H 12H 20 INTTA0 8 bit timer0 004CH FFFF4CH 13H 21 INTTA1 8 bit timer1 0050H FFFF50H 14H 22 INTTA2 8 bit rimer2 0054H FFFF54H 15H 23 INTTA3 8 bit timer3 0058H FFFF58H 16H 24 INTRX0 serial reception channel 0 005CH FFFF5CH 17H 25 INTTX0 serial transmission channel 0 0060H FFFF60H 18H ...

Page 43: ... addition the micro DMA start vector register DMAnV is cleared to 0 the next micro DMA is disabled and micro DMA processing completes If the decreased result is other than 0 the micro DMA processing completes if it isn t specified the say later burst mode In this case the micro DMA transfer end interrupt INTTC0 to INTTC3 aren t generated If an interrupt request is triggered for the interrupt sourc...

Page 44: ...pt for Counter mode the same as for other modes The conditions for this cycle are based on an external 16 bit bus 0 waits trandfer source transfer destination addresses both even numberd values Output Input Trasger destination address Next 2 Next 1 state D0 to 15 X1 A0 to 23 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 note1 note2 RD WR HWR Trasfer source address Figure 3 4 2 Timing for micro DMA cycle States ...

Page 45: ...data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA Symbol NAME Address 7 6 5 4 3 2 1 0 DMA Request DMAR3 DMAR2 DMAR1 DMAR0 R W DMAR DMA Request Register 89h no RMW 0 0 0 0 3 Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU Data setting for these ...

Page 46: ...r Transfer Source Address DEC Mode Memory to I O DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn is generated 100 00 Byte transfer 8 states 1000 ns 01 Word transfer 12 sates 1500 ns 10 4 byte transfer Fixed Address Mode I O to I O DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn is generated 101 00 Counter Mode For counting number of times interrupt is generated DMASn DMASn 1 DMACn DMACn 1 If DMA...

Page 47: ...same level are generated at the same time the default priority the interrupt with the lowest priority or in other words the interrupt with the lowest vector value is used to determine which interrupt request is accepted first The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has...

Page 48: ...H V 3CH V 40H V 44H V 48H V 4CH D Q CLR Y1 Y2 Y3 Y4 Y5 Y6 A B C Dn Dn 1 Dn 2 Interrupt request F F Interrupt vector read Micro DMA acknowledge Interrupt request F F Dn 3 A B C interrupt vector read D2 D3 D4 D5 D6 D7 Selector S Q R 0 1 2 3 A B D0 D1 Interrupt vector read Interrupt mask F F Micro DMA request HALT release NMI if INTRQ2 0 IFF 2 0 then 1 INTRQ2 0 IFF2 0 Interrupt level detect RESET EI ...

Page 49: ...2M2 IA2M1 IA2M0 R R W R R W INTEALM 23 INTALM 2 INTALM 3 Enable 94h 0 0 0 0 0 0 0 0 INTTA1 TMRA1 INTTA0 TMRA0 ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0 R R W R R W INTETA01 INTTA0 INTTA1 Enable 95h 0 0 0 0 0 0 0 0 INTTA3 TMRA3 INTTA2 TMRA2 ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0 R R W R R W INTETA23 INTTA2 INTTA3 Enable 96h 0 0 0 0 0 0 0 0 INTRTC IRC IRM2 IRM1 IRM0 R R W ...

Page 50: ...NTET C01 INTTC0 INTTC1 Enable 9BH 0 0 0 0 0 0 0 0 INTTC3 INTTC2 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R W R R W INTET C23 INTTC2 INTTC3 Enable 9CH 0 0 0 0 0 0 0 0 INTP1 INTP0 IP1C IP1M2 IP1M1 IP1M0 IP0C IP0M2 IP0M1 IP0M0 R R W R R W INTE P01 INTP0 INTP1 Enable 9DH 0 0 0 0 0 0 0 0 Interrupt request flag lxxM2 lxxM1 lxxM0 Function Write 0 0 0 Disables interrupt requests 0 0 1 Sets ...

Page 51: ...Interrupt Clear Control 88H no RMW Interrupt Vector 4 Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source When the micro DMA transfer counter value reaches zero the micro DMA transfer end interrupt corresponding ...

Page 52: ...tor DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R W DMA3V DMA3 Start Vector 83H 0 0 0 0 0 0 5 Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst Symbol NAME Address 7 6 5...

Page 53: ... the interrupt request flag is cleared automatically INT0 Level Mode If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1 INT0 must then be held at 1 until the interrupt response sequence has been completed If INT0 is set to Level Mode so as to release a Halt state INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the Halt state is released Henc...

Page 54: ...t 5 P54 1 I O PU Bit BUSRQ P55 1 I O PU Bit BUSAK P56 1 I O PU Bit WAIT Port 6 P60 1 Output Fixed CS0 P61 1 Output Fixed CS1 P62 1 Output Fixed CS2 CS2A P63 1 Output Fixed CS3 P64 1 Output Fixed EA24 CS2B P65 1 Output Fixed EA25 CS2C P66 1 Output Fixed CS2D P67 1 Output Fixed CS2E Port 7 P70 P71 P72 1 1 1 I O I O I O PU PU Bit Bit Bit SCK OPTRX0 SO SDA OPTTX0 SI SCL Port 8 P80 to P87 8 Input Fixed...

Page 55: ...put Without PU 0 0 Port 5 P56 WAIT input With PU 1 0 None None P60 to P64 Output port X 0 0 P60 CS0 output X 1 P61 CS1 output X 1 None CS2 output X 1 0 P62 CS2A output X X 1 P63 CS3 output X 1 None EA24 output X 1 0 P64 CS2B output X X 1 EA25 output X 1 0 P65 CS2C output X X 1 P66 CS2D output X 0 1 Port 6 P67 CS2E output X None 0 1 Input port without PU 0 0 0 0 Input port With PU 1 0 0 0 P70 to P7...

Page 56: ... Note2 1 1 1 Port C PC5 CTS1 input Note2 1 0 0 PD5 to PD7 Output port X 0 PD5 SCOUT output X 1 ALARM output 1 1 PD6 MLDALM output 0 1 Port D PD7 MLDALM output X None 1 Input port Without PU 0 0 0 Input port with PU 1 0 0 PZ2 to PZ3 Output port X 1 0 PZ2 HWR output X 1 1 Port Z PZ3 R W output X 1 1 None note1 PORT1 is only use for PORT or DATA bus D8 to D15 by setting AM1 and AM0 pins note2 As for ...

Page 57: ... ON OFF by programmable when they are used as the input ports When they are used as output ports they cannot be turned ON OFF in software Table 3 5 4 shows the pin states after the bus has been released Table 3 5 4 Pin states after bus release The pin state when the bus is released Pin name Port mode Function mode D0 D7 Become high impedance Hz D8 D15 P10 P17 The state is not changed do not become...

Page 58: ...l register P1CR Resetting the control register P1CR to 0 and sets Port 1 to input mode In addition to functioning as a general purpose I O port Port 1 can also function as an address data bus D8 to 15 Internal data bus Direction control on bit basis P1CR write P10 to P17 D8 to D15 Output buffer Reset P1 Read Output Latch P1 write Port 1 Figure 3 5 1 Port 1 ...

Page 59: ...A23 Each bit can be set individually for address bus using the function register P2FC Resetting sets all bits of the function register P2FC to 1 and sets Port 2 to address bus Internal data bus Function control on bits basis P2FC write P20 to P27 A16 to A23 Output buffer Reset P2 read Output latch P2 write Port 2 selector S A B S Internal A16 to A23 Figure 3 5 2 Port 2 ...

Page 60: ...ction 0 IN 1 OUT Port 2 Register 7 6 5 4 3 2 1 0 bit Symbol P27 P26 P25 P24 P23 P22 P21 P20 Read Write R W After Reset Output latch register is set to 1 Port 2 Function Register 7 6 5 4 3 2 1 0 bit Symbol P27F P26F P25F P24F P23F P22F P21F P20F Read Write W After Reset 1 1 1 1 1 1 1 1 Function 0 Port 1 Address bus A23 to A16 P0 0000H P1 0001H Port 1 I O setting 0 Input 1 Output P1CR 0004H P2FC 000...

Page 61: ...n register P5FC to 0 and sets P54 to P56 to input mode with pull up register In addition to functioning as a general purpose I O port Port 5 also functions as I O for the CPU s control status signal Function conrtol on bit basis S Output latch P55 BUSAK Selector Internal Data BUS Direction control on bit basis P5CR Write P ch Programmable Pull up Reset P5FC Write P5 Write Output buffer P5 Read S A...

Page 62: ...ol on bit basis P5CR Write P ch Programmable Pull up Reset P56 WAIT Function contorol on bit basis S Output Latch P5FC Write P5 Write P54 BUSRQ P5 Read Internal Data Bus Direction control on bit basis P5CR Write P ch Programmable Pull up Reset Internal BUSRQ Output buffer Figure 3 5 5 Port 5 P56 P54 ...

Page 63: ...0 PORT 1 BUSAK 0 PORT 1 BUSRQ P5FC 000BH P5 000DH II O setting 0 Input 1 Output note1 Read modify write is prohibited for register P5CR P5FC note2 When port5 is used in the input mode P5 register controls the built in pull up resistor Read modify write is prohibited in the input mode or the I O mode Setting the built in pull up resistor may be depended on the States of the input pin note3 When P56...

Page 64: ... write P6 write S A B Function control 2 on bit basis P6FC2 write 1 1 CS2A 1 CS2B C Figure 3 5 7 Port 6 Port 6 Register 7 6 5 4 3 2 1 0 bit Symbol P67 P66 P65 P64 P63 P62 P61 P60 Read Write R W After reset 1 1 1 1 1 0 1 1 Port 6 Function Register 7 6 5 4 3 2 1 0 bit Symbol P65F P64F P63F P62F P61F P60F Read Write W After reset 0 Function Always write 0 0 PORT 1 EA25 0 PORT 1 EA24 0 PORT 1 CS3 0 PO...

Page 65: ...espective functions Resetting resets the P7FC P7FC2 to 0 and sets all bits to input ports 1 Port70 SCK OPTRX0 Port70 is a general purpose I O port It is also used as SCK clock signal for SIO mode and OPTRX0 receive input for IrDA mode of SIO0 Used as OPTRX0 it is possible to logical invert by P7 P70 0 For PortC1 RXD0 or OPTRX0 is used P7FC2 P70F2 Internal data bus Selector A B S Selector A B S P70...

Page 66: ... of SIO0 Used as OPTTX0 it is possible to logical invert by P7 P71 0 Open drain possible P7ODE ODEP71 SO output Internal data bus Selector A B S Selector A B S P71 SO SDA OPTTX0 P7 read Direction control on bit basis P7CR write Function control on bit basis P7FC write S Output latch P7 write Reset SDA input Programable pull up Function control 2 on bit basis P7FC2 write C logical invert TXD0 outpu...

Page 67: ... C mode for serial bus interface and input for release hard protect Open drain possible P7ODE ODEP72 SCL output Internal data bus Selector A B S Selector A B S P72 SI SCL P7 read Direction control on bit basis P7CR write Function control on bit basis P7FC write S Output latch P7 write Reset SI input SCL input P ch Programable Pull up Figure 3 5 11 Port 72 ...

Page 68: ...ion 0 PORT 1 SCL output 0 PORT 1 SDA SO output 0 PORT 1 SCK output Port 7 Function Register 2 7 6 5 4 3 2 1 0 bit Symbol P72F2 P71F2 P70F2 Read Write W After reset 0 Function Always write to 0 0 P71F 1 OPTTX0 SIO0 RXD Pin select 0 RXD0 PC1 1 OPTRX0 P70 P7FC 0017H P7 0013H P7CR 0016H P7FC2 001CH Port 7 ODE Register 7 6 5 4 3 2 1 0 bit Symbol ODEP72 ODEP71 Read Write After reset 0 0 Function 0 3 STA...

Page 69: ... Read Conversion Result Register A D Converter Channel Selector Port 8 read Port 8 P80 to P87 AN0 to AN7 ADTRG for P83 only Figure 3 5 13 Port 8 Port 8 Register 7 6 5 4 3 2 1 0 Bit Symbol P87 P86 P85 P84 P83 P82 P81 P80 Read Write R After reset Input mode note The input channel selection of A D Converter and the permission of ADTRG input are set by A D Converter mode register ADMOD1 P8 0018H Figur...

Page 70: ...on is establishes by IIMC register in the interrupt controller Timer output function and external interrupt function can be enabled by writing 1 to the corresponding bits in the Port B Function Register PBFC Resetting resets all bits of the registers PBCR and PBFC to 0 and sets all bits to be input ports 1 PB0 to PB2 TA0IN PB1 TA1OUT PB2 TA3OUT PB read Timer F F OUT PB read Internal data bus Selec...

Page 71: ...S Output latch PB write Reset PBFC write Level edge select Raising Falling select INT0 IIMC I0LE I0EDGE Figure 3 5 16 Port B3 Internal data bus Direction Control on bits basis Reset PBCR write S Out latch PB write PB4 PB6 INT1 INT3 Selector PB read Raising Falling edge detection PAFC PA4F PA5F PA6F IIMC I1EDGE I2EDGE I3EDGE S B A Y INT1 INT3 to Figure 3 5 17 Port B4 to B6 ...

Page 72: ...n Register 7 6 5 4 3 2 1 0 bit Symbol PB6F PB5F PB4F PB3F PB2F PB1F Read Write W After Reset 0 Function 0 PORT 1 INT3 0 PORT 1 INT2 0 PORT 1 INT1 0 PORT 1 INT0 0 PORT 1 TA3OUT 0 PORT 1 TA1OUT PBFC 0025H PB 0022H PBCR 0024H note1 Read Modify Write is prohibited for the registers PBCR and PBFC note2 PB0 TA0IN pin does not have a register changing PORT FUNCTION For example when it is used as an input...

Page 73: ...all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports 1 Port C0 C3 TXD0 TXD1 As well as functioning as I O port pins port C0 and C3 can also function as serial channel TXD output pins In case of use TXD0 TXD1 it is possible to logical invert by setting the register PC PC0 PC3 And port C0 to C3 have a programmable open drain function which can be controled by the register...

Page 74: ... Reset S Output latch Internal data bus PC write Logical invert Figure 3 5 20 Port C1 and C4 3 Port C2 CTS0 SCLK0 C5 CST1 SCLK1 Port C2 and C4 are I O port pins and can also is used as CTS input or SCLK input output for the serial channels In case of use CTS SCLK it is possible to logical invert by setting the register PC PC2 PC5 Selector A B S Selector A B S PC2 SCLK0 CTS0 PC5 SCLK1 CTS1 SCLK0 1 ...

Page 75: ... 0 0 Function 0 PORT 1 SCLK1 Output 0 PORT 1 TXD1 0 PORT 1 SCLK0 Out put 0 PORT 1 TXD0 Port C ODE Register 7 6 5 4 3 2 1 0 bit Symbol ODEPC3 ODEPC0 Read Write W W After Reset 0 0 Function TXD1 0 CMOS 1 Open Drain TXD0 0 CMOS 1 Open Drain PCFC 0027H PC 0023H PCCR 0026H PCODE 0028H note1 Read Modify Write is prohibited for the registers PCCR PCFC and PCODE note2 PC1 RXD0 PC4 RXD1 pins do not have a ...

Page 76: ...s used the function register PDFC Only PD6 has two output functions which ALARM and MLDALM This selection is used PD PD6 Resetting resets the function register PDFC to 0 and sets all ports to output ports Function control On bit basis Output latch PD read Reset PD7 MLDALM MLDALM Output buffer Selector PDFC write PD write S A B Internal data bus Figure 3 5 23 Port D Internal data bus Fs clock Reset...

Page 77: ...e 3 5 25 Port D Port D register 7 6 5 4 3 2 1 0 bit Symbol PD7 PD6 PD5 Read Write R W After Reset 1 1 1 Port D function register 7 6 5 4 3 2 1 0 bit Symbol PD7F PD6F PD5F Read Write W After Reset 0 Function 0 PORT 1 MLDALM 0 PORT 1 ALARM PD6 1 1 MLDALM PD6 0 0 PORT 1 SCOUT PD 0029H PDFC 002AH note Read Modify Write is prohibited for the registers PDFC Figure 3 5 26 Register for Port D ...

Page 78: ...oning as a general purpose I O port Port Z also functions as I O for the CPU s control status signal Resetting initializes PZ2 and PZ3 pins to input mode with pull up register When the PZ RDE register clearing to 0 outputs the RD strobe used for the peused static RAM of the RD pin even when the internal addressed If the RDE remains 1 the RD strobe signal is output only when the external address ar...

Page 79: ...s PZCR Write P ch Programmable Pull up Reset PZFC Write PZ Write Output buffer PZ Read S A B WHR Function conrtol on bit basis S Output latch PZ3 R W Selector Internal Data BUS Direction control on bit basis PZCR Write P ch Programmable Pull up Reset PZFC Write PZ Write Output buffer PZ Read S A B R W Figure 3 5 27 Port Z PZ2 PZ3 ...

Page 80: ...ad Write W After reset 0 0 Function Note Always fixed to 0 0 PORT 1 R W 0 PORT 1 HWR PZFC 007FH PZ 007DH Note 1 Read Modify write is prohibited for registers PZCR and PZFC Note 2 When Port Z is used in Input Mode the PZ register controls the built in pull up resistor Read Modify Write is prohibited in Input Mode or I O Mode Setting the built in pull up resistor may be depended on the states of the...

Page 81: ...3 are defined by the values in the Memory Start Address Registers MSAR0 to MSAR3 and the Memory Address Mask Registers MAMR0 to MAMR3 The Chip Select Wait Control Registers B0CS to B3CS and BEXCS should be used to specify the Master Enable Disable status the data bus width and the number of waits for each address area The input pin controlling these states is the bus wait request pin WAIT 3 6 1 Sp...

Page 82: ... between the start address and the start address register value Memory Start Address Registers for areas CS0 to CS3 7 6 5 4 3 2 1 0 bit Symbol S23 S22 S21 S20 S19 S18 S17 S16 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Determines A23 to A16 of start address MSAR0 00C8H MSAR1 00CAH MSAR2 00CCH MSAR3 00CEH Sets start addresses for areas CS0 to CS3 Figure 3 6 1 Memory Start Address Register 6...

Page 83: ... 7 6 5 4 3 2 1 0 bit Symbol V20 V19 V18 V17 V16 V15 V14 to 9 V8 Read Write R W After Reset 1 1 1 1 1 1 1 1 Function Sets size of CS0 area 0 used for address compare Range of possible settings for CS0 area size 256 bytes to 2 Mbytes Memory address mask register CS1 7 6 5 4 3 2 1 0 bit Symbol V21 V20 V19 V18 V17 V16 V15 to 9 V8 Read Write R W After Reset 1 1 1 1 1 1 1 1 Function Sets size of CS1 are...

Page 84: ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 F F F F S23 S22 S21 S20 S19 S18 S17 S16 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 V9 V8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 7 H H Memory end address Memory start address CSO area size 64 Kbytes Memory address mask register setting H MSAR0 MSMR0 Setting of 07H specifies a 64 Kbyte area Figure 3 6 4 Example showing how to set the CS0 area Af...

Page 85: ...hese addresses may be set as the start address Invalid start addresses 000000H 010000H 030000H 050000H 64K bytes 128K bytes 128K bytes This is not an integer multiple of the desired area size setting Hence none of these addresses can be set as the start address Table 3 6 1 Valid area sizes for each CS area Size bytes CS area 256 512 32 K 64 K 128 K 256 K 512 K 1 M 2 M 4 M 8 M CS0 CS1 CS2 CS3 note ...

Page 86: ...ved 001 1 wait 101 3 waits 010 1 wait N 110 4 waits 011 0 waits 111 8 waits Bit Symbol B3E B3OM1 B3OM0 B3BUS B3W2 B3W1 B3W0 Read Write W W After Reset 0 0 0 0 0 0 0 Functions 0 Disable 1 Enable Chip Select output waveform selection 00 For ROM SRAM 01 10 Don t care 11 Data bus width 0 16 bits 1 8 bits Number of waits 000 2 waits 100 reserved 001 1 wait 101 3 waits 010 1 wait N 110 4 waits 011 0 wai...

Page 87: ...namic bus sizing CPU Data Operand Data Bus Width Operand Start Address Memory Data Bus Width CPU Address D15 to D8 D7 to D0 8 bits 2n 0 xxxxx b7 b0 2n 0 Even number 16 bits 2n 0 xxxxx b7 b0 8 bits 2n 1 xxxxx b7 b0 8 bits 2n 1 Odd number 16 bits 2n 1 b7 b0 xxxxx 2n 0 xxxxx b7 b0 8 bits 2n 1 xxxxx b15 b8 2n 0 Even number 16 bits 2n 0 b15 b8 b7 b0 2n 1 xxxxx b7 b0 8 bits 2n 2 xxxxx b15 b8 2n 1 b7 b0 ...

Page 88: ...etting 101 3WAIT Inserts a wait of 3 state irrespective of the WAIT pin state 110 4WAIT Inserts a wait of 4 state irrespective of the WAIT pin state 111 8WAIT Inserts a wait of 8 state irrespective of the WAIT pin state A Reset sets these bits to 000 2 waits 4 Bus width and wait control for an area other than CS0 to CS3 The chip select wait control register BEXCS controls the bus width and number ...

Page 89: ...tus for CS0 to CS3 The CS0 to S3 pins can also function as pins P60 to P63 To output a Chip Select signal using one of these pins set the corresponding bit in the Port 6 Function Register P6FC to 1 If a CS0 to S3 address is specified which is actually an internal I O and RAM area address the CPU accesses the internal address area and no Chip Select signal is output on any of the CS0 to CS3 pins Se...

Page 90: ... 8 bit I O OE WE CS0 CS1 CS2 A0 A23 D8 D15 D0 D7 ＲＤＷＲ Figure 3 6 6 Example of external memory connection ROM uses 16 bit bus RAM and I O use 8 bit bus A Reset clears all bits of the Port 6 Control Register P6CR and the Port 6 Function Register P6FC to 0 and disables output of the CS signal To output the CS signal the appropriate bit must be set to 1 Figure 3 6 7 Example of external memory connect...

Page 91: ...ion are controlled by 5bytes registers We call control registers SFRs Special Function Registers Each of the two modules TMRA01 and TMRA23 can be operated independently All modules operate in the same manner hence only the operation of TMRA01 is explained here The contents of this chapter are as follows 3 7 1 Block diagrams 3 7 2 Operation of each circuit 3 7 3 SFRs 3 7 4 Operation in each mode 1 ...

Page 92: ... timer register TA0REG TA01RUN TA0RDE TA01RUN TA0RUN φT1 φT4 φT16 2 n 1 Over flow TMRA0 Interrupt output INTTA0 TA01MOD TA01M1 TA01M 0 TMRA0 Match output TA0TRG Selector φT1 φT16 φT256 Internal bus TA01MOD TA0CLK1 TA0CLK10 TA01MOD TA1CLK1 TA1CLK 0 Match detect TMRA1 Interrupt output INTTA1 TA01RUN TA1RUN Timer Flip Flop TA1FF TA1FFCR Timer flip flop output TA1OUT 512 256 128 64 32 16 8 4 2 φT1 φT4...

Page 93: ... Over flow TMRA2 Interrupt output INTTA2 TA23MOD TA23M1 TA23M10 TMRA2 Match output TA2TRG Selector φT1 φT16 φT256 Internal bus TA23MOD TA3CLK1 0 Match detect TMRA3 Interrup outptu INTTA3 TA23RUN TA3RUN Timer flip flop TA3FF TA3FFCR Timer flip flop output TA3OUT 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Prescaler TA23RUN TA23PRUN Internal bus 8 bit Up Counter UC3 8 bit Timer Register TA2REG TA2...

Page 94: ...fc 29 32 µs fc 213 512 µs 011 fc 8 fc 26 4 0 µs fc 28 16 µs fc 210 64 µs fc 214 1024 µs 00 fFPH 100 fc 16 fc 27 8 0 µs fc 29 32 µs fc 211 128 µs fc 215 2048 µs 0 fc 10 fc 16 CLOCK XXX fc 27 8 0 µs fc 29 32 µs fc 211 128 µs fc 215 2048 µs xxx Don t care 2 Up counters UC0 and UC1 These are 8 bit binary counters which count up the input clock pulses for the clock specified by TA01MOD The input clock ...

Page 95: ...Mode or at the start of the PPG cycle in PPG Mode Hence the double buffer cannot be used in Timer Mode A Reset initializes TA0RDE to 0 disabling the double buffer To use the double buffer write data to the timer register set TA0RDE to 1 and write the following data to the register buffer Figure 3 7 3 show the configuration of TA0REG Selector Y S A B Write Shift trigger Write to TA0REG 2n 1 overflo...

Page 96: ... the match detects signal 8 bit comparator output of each interval timer Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR TAFF1IE in the Timer Flip Flop Control Register A Reset clears the value of TA1FF1 to 0 Writing 01 or 10 to TA1FFCR TAFF1C 1 0 sets TA1FF to 0 or 1 Writing 00 to these bits inverts the value of TA1FF this is known as software inversion Th...

Page 97: ...TA1RUN Run Timer 1 TA0RUN Run Timer 0 note The values of bits 4 5 6 of TA01RUN are undefined when read TMRA23 Run Register 7 6 5 4 3 2 1 0 Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN Read Write R W R W After Reset 0 0 0 0 0 Function Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate Timer Run Stop control 0 Stop Clear 1 Run count up TA23RUN 0108H Timer Run Stop control 0 Stop Clear 1 Run ...

Page 98: ... for TMRA0 00 TA0IN pin 01 φT1 10 φT4 11 φT16 00 TA0IN external input 01 φT1 prescaler 10 φT4 prescaler 11 φT16 prescaler TA01MOD TA01M1 TA01M0 01 TA01MOD TA01M1 TA01M 0 01 00 Comparator output from TMRA0 01 φT1 10 φT16 11 φＴ256 Overflow output from TMRA0 16 Bit Timer Mode 00 reserved 01 26 1 clock source 10 27 1 clock source 11 28 1 clock source 00 Two 8 bit timers 01 16 bit timer 10 8 bit PPG 11...

Page 99: ...clock for TMRA2 00 reserved 01 φT1 10 φT4 11 φT16 00 Do not set 01 φT1 prescaler 10 φT4 prescaler 11 φT16 prescaler TA23MOD TA23M1 TA23M0 01 TA23MOD TA23M1 TA23M0 01 00 Comparator output from TMRA2 01 φT1 10 φT16 11 φＴ256 Overflow output from TMRA2 16 Bit Timer Mode 00 reserved 01 26 1 clock source 10 27 1 clock source 11 28 1 clock source 00 Two 8 bit timers 01 16 bit timer 10 8 bit PPG 11 8 bit ...

Page 100: ...trol for inversion 0 Disable 1 Enable TA1FF Inversion select 0 TMRA0 1 TMRA1 0 Inversion by TMRA0 1 Inversion by TMRA1 0 Disabled 1 Enabled 00 Inverts the value of TA1FF 01 Sets TA1FF to 1 10 Clears TA1FF to 0 11 Don t care Control of TA1FF TA1FFCR 0105H Inverse signal for Timer Flop Flop 1 TA1FF Don t care except in 8 Bit Timer Mode Inversion of TA1FF Read Modify Write instructions are prohibited...

Page 101: ...trol for inversion 0 Disable 1 Enable TA3FF Inversion select 0 TMRA2 1 TMRA3 0 Inversion by TMRA2 1 Inversion by TMRA3 0 Disabled 1 Enabled 00 Inverts the value of TA3FF 01 Sets TA3FF to 1 10 Clears TA3FF to 0 11 Don t care Control of TA3FF TA3FFCR 010DH Inverse signal for Timer Flip Flop 3 TA3FF Don t care except in 8 Bit Timer Mode Inversion of TA3FF Read Modify Write instructions are prohibited...

Page 102: ...ounting Example To generate an INTTA1 interrupt every 20 µseconds at fc 16 MHz set each register as follows Clock state System clock High frequency fc Prescaler clock fFPH MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 1 0 X X Select 8 Bit Timer Mode and select φT1 0 5 µs at fc 16 MHz as the input clock TA1REG 0 0 1 0 1 0 0 0 Set TA1REG to 20 µs φT1 40 28H INTET...

Page 103: ...ck fFPH 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 Select 8 Bit Timer Mode and select φT1 0 5 µs at fc 16 MHz as the input clock TA1REG 0 0 0 0 0 0 1 1 Set the timer register to 3 0 µs φT1 2 3 TA1FFCR X X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detects signal from TMRA1 PBCR X 1 PBFC X 1 X Set PB1 to function as the TA1OUT pin TA01RUN X ...

Page 104: ...Timer Mode the overflow output from TMRA0 is used as the input clock for TMRA1 regardless of the value set in TA01MOD TA01CLK1 TA01CLK0 Table 3 7 2 shows the relationship between the timer interrupt cycle and the input clock selection LSB 8 bit set to TA0REG and MSB 8 bit is for TA1REG Please keep setting TA0REG first because setting data for TA0REG inhibit its compare function and setting data fo...

Page 105: ...if inversion is enabled the value of the timer flip flop TA1FF is inverted Example When TA1REG 04H and TA0REG 80H 0080H 0180H 0280H 0380H 0480H Value of up counter UC1 UC0 Inversion TMRA0 comparator match detect signal Interrupt INTTA1 0000H Timer output TA1OUT Figure 3 7 11 Timer output by 16 Bit Timer Mode 3 8 Bit PPG Programmable Pulse Generation Output Mode Square wave pulses can be generated ...

Page 106: ...N 8 bit up counter UC 0 Comparator Comparator TA0REG Register Buffer TA01RUN TA0RDE TA1REG Internal bus TA1FF INTTA0 INTTA1 Inversion TA01MOD TA0CLK1 0 Selector TA1FFCR TAFF1IE TA0REG WR TA1OUT Figure 3 7 13 Block diagram of 8 Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0 Use of the ...

Page 107: ...28H The duty is to be set to 1 4 t 1 4 20 µsec 1 4 5 µsec 5 µsec 0 5 µsec 10 Therefore set TA0REG 10 0AH 7 6 5 4 3 2 1 0 TA01RUN 0 X X X 0 0 0 Stop TMRA0 and TMRA01 and clear it to 0 TA01MOD 1 0 X X X X 0 1 Set the 8 bit PPG mode and select φT1 as input clock TA0REG 0 0 0 0 1 0 1 0 Write 0AH TA1REG 0 0 1 0 1 0 0 0 Write 28H TA1FFCR X X X X 0 1 1 X Set TA1FF enabling both inversion and the double b...

Page 108: ... UC0 is cleared when 2n 1 counter overflow occurs The following conditions must be satisfied before this PWM mode can be used Value set in TA0REG value set for 2n 1 counter overflow Value set in TA0REG 0 TA1OUT 2n 1 overflow INTTA0 interrupt tPWM PWM cycle TA0REG and UC0 match Figure 3 7 15 8 bit PWM waveforms Figure 3 7 16 shows a block diagram representing this mode TA01MOD PWM01 PWM0100 TA1FFCR...

Page 109: ...c 63 5 µsec Clock state System clock High frequency fc Clock gear 1 fc Prescaler clock fFPH To achieve a 63 5 µs PWM cycle by setting φT1 to 0 5 µsec at fc 16 MHz 63 5 µsec 0 5 µsec 127 2n 1 Therefore n should be set to 7 Since the low level period is 36 0 µsec when φT1 0 5 µsec set the following value for TA0REG 36 0 µsec 0 5 µsec 72 48H MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA0 and clea...

Page 110: ... 32 64 ms 0 fc 10 fc 16 clock XXX 504 µs 2016 µs 8064 µs 1016 µs 4064 µs 16 256 ms 2040 µs 8160 µs 32 64 ms XXX Don t care 5 Settings for each mode Table 3 7 4 shows he SFR settings for each mode Table 3 7 4 Timer mode setting registers Register name TA01MOD TA1FFCR Bit Symbol TA01M1 TA01M 0 PWM01 00 TA1CLK1 0 TA0CLK1 0 TAFF1IS Function Timer mode PWM cycle Upper timer input clock Lower timer inpu...

Page 111: ...S WAIT Set up AH C0 FF to CS2 Set up AH 80 FF to CS2 Program ROM Used CS pin CS2 CS2A Maximum memory size 64MB 64MB 1pcs 64MB 16MB 4pcs Used local area BANK number LOCAL3 AH 80 BF 4MB 16BANK LOCAL3 AH 80 BF 4MB 24BANK Setting CS WAIT Set up AH 80 BF to CS3 Set up AH 80 FF to CS2 Data ROM Used CS pins CS3 EA24 EA25 CS2B CS2C CS2D CS2E Maximum memory size COMMON1 2MB 14MB 16MB 1pcs Used local area B...

Page 112: ... fixed the address of a local area cannot be changed 000000H LOCAL0 COMMON0 LOCAL1 COMMON1 LOCAL3 LOCAL2 COMMON2 Vector Area Internal Area Overlapped with COMMON Area 0 1 2 14 15 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1MB 100000H 200000H 400000H 1MB 2MB 2MB 2MB 4MB 2MB 2MB 256B 600000H 800000H C00000H E00000H FFFF00 FFFFFF CS0 CS0 CS1 CS3 CS2 CS0 CS0 CS1 CS3 EA24 EA25 CS2 Address Size Memory map Bank CS ...

Page 113: ...L0 LOCAL1 LOCAL2 CS2A for Program ROM 16MB LOCAL3 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 91C824 800000H 1000000H Overlapped with COMMON Area BANK8 BANK9 BANK10 BANK11 BANK12 BANK13 BANK14 BANK15 CS2E CS2C CS2D 000000H 1000000H 000000H 1000000H Internal Area Figure 3 8 1 2 Physical address map T...

Page 114: ...aldata bus Selector 0 L0E L1E L2E L3E CS2A CS2B CS2C CS2D CS2E EA23 to EA21 EA23 to EA21 EA26 to EA22 A23 to A20 Physical Address WA26 to WA7 A2 to A16 LOCAL3 Area detect signal VA26 to VA20 Physical address CPU out Address A19 to A7 To external address bus pins CPU out Address A23 to A16 LOCAL3 area detect signal LOCAL3 register Figure 3 8 2 1 Block diagram of MMU ...

Page 115: ...bit Symbol L2E L2EA23 L2EA22 L2EA21 Read Write R W R W After reset 0 0 0 0 Function Use BANK for LOCAL2 0 disable 1 enable Setting BANK number for LOCAL2 LOCAL3 register 7 6 5 4 3 2 1 0 bit Symbol L3E L3EA26 L3EA25 L3EA24 L3EA23 L3EA22 Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 Function Use BANK for LOCAL3 0 disable 1 enable 01000 to 01011 CS2D 00000 to 00011 CS2B 00100 to 00111 CS...

Page 116: ...usly set up by the CS WAIT controller When CPU outputs logical address of the local area MMU outputs physical address to the outside address bus pin according to value of bank setting register Access of external memory becomes possible therefore Please do not use as bank that overlaps with another bank since this common area overlaps with either of eight banks of local area on the physical map Exa...

Page 117: ... Control signals D 0 7 D 0 7 A0 A0 A1 A7 A1 A2 A7 A2 Figure 3 8 4 1 H W Setting Example At Figure 3 8 4 1 it shows example of connection TMP91C824 and some memories Program ROM MROM 16Mbyte Data ROM MROM 64Mbyte Data RAM SRAM 8Mbyte 8bit bus Option ROM Flash 16Mbyte In case of 16bit bus memory connection it need to shift 1bit address bus from TMP91C824 and 8bit bus case direct connection address b...

Page 118: ...XCS 00H Other 16bit 2wait don t care Port LD P6FC 3FH CS0 CS3 EA24 EA25 port6 setting Figure 3 8 4 2 Bank Operation S W Example1 Secondly it shows example of initial setting at Figure 3 8 4 2 Because CS0 connect to RAM 8bit bus 8Mbyte it need to set 8bit bus At this example it set 1 wait setting In the same way CS1 set to 16bit bus and 2 wait CS2 set 16bit bus and 0 wait CS3 set 16bit bus and 3 wa...

Page 119: ...000H Data ROM Start address at Bank5 of Local3 dw 5555H ORG 1800000H Data ROM Start address at Bank6 of Local3 ORG 1C00000H Data ROM Start address at Bank7 of Local3 ORG 2000000H Data ROM Start address at Bank8 of Local3 dw AAAAH ORG 2400000H Data ROM Start address at Bank9 of Local3 ORG 2800000H Data ROM Start address at Bank10 of Local3 ORG 2C00000H Data ROM Start address at Bank11 of Local3 ORG...

Page 120: ... Physical address of Local2 ORG E00200H LD LOCAL1 84H Local1 Bank4 set 80xxxxH JP 400000H Jump to Bank4 800000H Physical address of Local1 ORG FFFFFFH Program ROM End address at Bank7 Common2 of Local2 CS1 ORG 000000H Program ROM Start address at Bank0 of Local1 ORG 200000H Program ROM Start address at Bank1 of Local1 ORG 400000H Program ROM Start address at Bank2 of Local1 ORG 600000H Program ROM...

Page 121: ...flict with is possible When two kinds or more logical addresses to show common area exist management of BANK is confused We recommends not to use The BANK setting BANK address and common address conflict with When it jump to one memory from other different memory it can set same as the last time setting It needs to write to BANK register of LOCAL1 area upper 3 bit address of jumping point After se...

Page 122: ... be used independently Both channels operate in the same fashion except for the following points hence only the operation of Channel 0 is explained below Table 3 9 1 Differences between Channels 0 to 1 Channel 0 Channel 1 Pin Name TXD0 PC0 RXD0 PC1 0 CTS SCLK0 PC2 TXD1 PC3 RXD1 PC4 CTS1 SCLK1 PC5 IrDA Mode Yes No This chapter contains the following sections 3 9 1 Block diagram 3 9 2 Operation of e...

Page 123: ... 7 7 7 bit 0 1 2 3 4 5 6 start 8 7 stop bit 0 1 2 3 4 5 6 start stop Wake up bit 8 7 When bit 8 1 address select code is denoted When bit 8 0 data is denoted Mode 0 I O Interface Mode Transfer direction Mode 1 7 Bit UART Mode Mode 2 8 Bit UART Mode Mode 3 9 Bit UART Mode No parity Parity No parity Parity 7 bit 0 1 2 3 4 5 6 Figure 3 9 1 Data formats ...

Page 124: ... Transmision counter UART only 16 Transmission Control Receive Control Receive Buffer1 shift register RB8 Receive Buffer2 SC0BUF Error flag SIOCLK UART Mode SC0MOD0 SC1 SC0 SC0MOD0 SM1 SM0 TB8 Transmission Buffer SC0BUF INT request INTRX0 INTTX0 SC0CR OERR PERR FERR CTS0 concurrent with PC2 SC0MOD0 CTSE RXD0 concurrent with PC1 PE SC0CR EVEN TXDCLK SC0MOD0 RXE Parity control Serial clock generatio...

Page 125: ...nter UART only 16 Transmission Control Receive Control Receive Buffer1 shift register RB8 Receive buffer2 SC1BUF Error flag SIOCLK UART Mode SC1MOD0 SC1 SC0 SC1MOD0 SM1 SM0 TB8 Transmission Buffer SC1BUF INT request INTRX1 INTTX1 SC1CR OERR PERR FERR CTS1 concurrent with PC5 SC1MOD0 CTSE RXD1 concurrent with PC4 PE SC1CR EVEN TXDCLK SC0MOD0 RXE Parity Control Serial clock generation circuit SCLK1 ...

Page 126: ... 3 9 2 Prescaler Clock Resolution to Baud Rate Generator Prescaler Output Clock Resolution Select System Clock SYSCK Select Prescaler Clock PRCK1 to PRCK0 Gear Value GEAR2 to GEAR0 φT0 φT2 φT8 φT32 1 fs XXX fs 22 fs 24 fs 26 fs 28 000 fc fc 22 fc 24 fc 26 fc 28 001 fc 2 fc 23 fc 25 fc 27 fc 29 010 fc 4 fc 24 fc 26 fc 28 fc 210 011 fc 8 fc 25 fc 27 fc 29 fc 211 00 fFPH 100 fc 16 fc 26 fc 28 fc 210 ...

Page 127: ...0ADD BR0K3 to BR0K0 are ignored The baud rate generator divides the selected prescaler clock by N which is set in BR0CK BR0S3 to BR0S0 N 1 2 3 16 2 When BR0CR BR0ADDE 1 The N 16 K 16 division function is enabled The baud rate generator divides the selected prescaler clock by N 16 K 16 using the value of N set in BR0CR BR0S3 to BR0S0 N 2 3 15 and the value of K set in BR0ADD BR0K3 to R0K0 K 1 2 3 1...

Page 128: ...put clock frequency φT0 the frequency divider N BR0CR BR0S3 to BR0S0 7 K BR0ADD BR0K3 to BR0K0 3 and BR0CR BR0ADDE 1 the baud rate in UART Mode is as follows Clock state System clock High frequency fc Clock gear 1 fc Prescaler clock System clock Baud Rate 16 4 8 106 4 7 13 16 16 9600 bps Table 3 9 3 Table 3 9 4 show examples of UART Mode transfer rates Additionally the external clock input is avai...

Page 129: ...system clock the clock gear is set for fc 1 and the system clock is the prescaler clock input fFPH Table 3 9 4 UART baud rate selection When TMRA0 with input Clock φT1 is used fc TA0REG0 12 288 MHz 12 MHz 9 8304 MHz 8 MHz 6 144 MHz 1H 96 76 8 62 5 48 2H 48 38 4 31 25 24 3H 32 31 25 16 4H 24 19 2 12 5H 19 2 9 6 8H 12 9 6 6 AH 9 6 4 8 10H 6 4 8 3 14H 4 8 2 4 Method for calculating the transfer rate ...

Page 130: ...ses to receive 1 bit of data each data bit is sampled three times on the 7th 8th and 9th clock cycles The value of the data bit is determined from these three samples using the majority rule For example if the data bit is sampled respectively as 1 0 and 1 on 7th 8th and 9th clock cycles the received data bit is taken to be 1 A data bit sampled as 0 0 and 1 is taken to be 0 5 Receiving control In I...

Page 131: ...9 Bit UART Mode the wake up function for the slave controller is enabled by setting SC0MOD0 WU to 1 in this mode INTRX0 interrupts occur only when the value of SC0CR RB8 is 1 7 Transmission counter The transmission counter is a 4 bit binary counter which is used in UART Mode and which like the receiving counter counts the SIOCLK clock pulses a TXDCLK pulse is generated every 16 SIOCLK clock pulses...

Page 132: ...here is no RTS pin a handshake function can be easily configured by setting any port assigned to be the RTS function The RTS should be output High to request send data halt after data receive is completed by software in the RXD interrupt routine RXD RTS any port Receiver TXD CTS 91C824 Sender 91C824 Figure 3 9 5 Handshake function Timing to writing to the Transmission Buffer CTS 13 14 15 16 1 2 3 ...

Page 133: ...d after the data has been transferred to Receiving Buffer 2 SC0BUF and then compared with SC0BUF RB7 in 7 Bit UART Mode or with SC0CR RB8 in 8 Bit UART Mode If they are not equal a Parity error is generated and the SC0CR PERR flag is set 11 Error flags Three error flags are provided to increase the reliability of data reception 1 Overrun error OERR If all the bits of the next data item have been r...

Page 134: ...Parity 8 Bit 7 Bit Parity 7 Bit Interrupt timing Just before stop bit is transmitted Just before stop bit is transmitted Just before stop bit is transmitted I O interface SCLK Output Mode Immediately after rise of last SCLK signal See figure 3 9 19 Transmission Interrupt timing SCLK Input Mode Immediately after rise of last SCLK signal Rising Mode or immediately after fall in Falling Mode See figu...

Page 135: ...nput Serial transmission clock source UART 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock SCLK0 input Note The clock selection for the I O interface mode is controlled by the serial bontrol register SC0CR Serial Transmission Mode 00 I O Interface Mode 01 7 bit mode 10 8 bit mode 11 UART mode 9 bit mode Wake up function 9 Bit UART Other Modes 0 In...

Page 136: ...Internal clock fSYS 11 External clcok SCLK0 input Serial transmission clock source for UART 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock SCLK1 input Serial Transmission Mode 00 I O Interface Mode 01 7 bit mode 10 8 bit mode 11 UART mode 9 bit mode Wake up function 9 Bit UART Other Modes 0 Interrupt generated when data is received 1 Interrupt ge...

Page 137: ...ck selection Framing Error flag Parity Error flag Overrun Error flag 0 Transmits and receivers data on rising edge of SCLK0 1 Transmits and receivers data on falling edge SCLK0 Edge selection for SCLK pin I O Mode 0 Disabled 1 Enabled Parity addition enable Even parity addition check 1 error 0 Baud rate generator 1 SCLK0 pin input cleared to 0 when read 0 Odd parity 1 Even parity Received data 8 n...

Page 138: ...lect Framing Error flag Parity Error flag Overrun Error flag 0 Transmits and receives data on rising edge of SCLK1 1 Transmits and receives data on falling edge of SCLK1 Edge selection for SCKL pin I O mode 0 Disabled 1 Enabled Parity addition enable Even parity addition check 1 error 0 Baud rate generator 1 SCLK1 pin input cleared to Zero when read 0 Odd parity 1 Even parity Received data bit 8 n...

Page 139: ...vided by N 16 K 16 Divided by N BR0CR 0203H 16 K 16 division enable 00 Internal clock φT0 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 Setting the input clock of baud rate generator 0 Disable 1 Enable Setting of the Divided frequency BR0ADD 0204H note1 The baud rate generator can be set 1 when UART mode and disable 16 K 16 division function Don t use in I O interface mode not...

Page 140: ...Disable Disabled by N 16 K 16 Divided by N BR1CR 020BH 16 K 16 division enable 00 Internal clock φT0 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 Input clock selection for baud rate generator 0 Disabled 1 Enabled Divided Frequency setting BR1ADD 020CH note1 The baud rate generator can be set 1 when UART mode and disable 16 K 16 division function Don t use in I O interface mod...

Page 141: ...B5 RB4 RB3 RB2 RB1 RB0 note Prohibit read modify write for SC0BUF Figure 3 9 13 Serial Transmission Receiving Buffer Registers SIO0 SC0BUF 7 6 5 4 3 2 1 0 Bit symbol I2S0 FDPX0 Read Write R W R W After Reset 0 0 Function IDLE2 0 Stop 1 Run duplex 0 half 1 full Figure 3 9 14 Serial Mode Control Register 1 SIO0 SC0MOD1 SC0MOD1 0205H ...

Page 142: ...B5 RB4 RB3 RB2 RB1 RB0 note Prohibit read modify write for SC1BUF Figure 3 9 15 Serial Transmission Receiving Buffer Registers SIO1 SC1BUF 7 6 5 4 3 2 1 0 bit Symbol I2S0 FDPX0 Read Write R W R W After Reset 0 0 Function IDLE2 0 Stop 1 Run duplex 0 half 1 full Figure 3 9 16 Serial Mode Control Register 1 SIO1 SC1MOD1 SC1MOD1 020DH ...

Page 143: ...tput extension TMP91C824 TXD SCLK Port Input extension TC74HC595 or equivalent TC74HC165 or equivalent TMP91C824 A B C D E F G H RxD SCLK Port Shift register A B C D E F G H SI SCK RCK QH CLOCK L S Shift register Figure 3 9 17 SCLK Output Mode connection example TMP91C824 TXD SCLK Port TMP91C824 A B C D E F G H RxD SCLK Port Shift register A B C D E F G H SI SCK RCK QH CLOCK L S External clock Out...

Page 144: ...e set to generate INTTX0 interrupt SCLK0 input SCLKS 0 Rising edge mode SCLK0 input SCLKS 1 Falling edge mode bit 0 bit 1 TXD0 ITX0C INTTX0 intterrupt reqest bit 5 bit 6 bit 7 Figure 3 9 20 Transmitting Operation in I O Interface Mode SCLK0 Input Mode Receiving In SCLK output mode the synchronous clock is outputted from SCLK0 pin and the data is shifted to Receiving Buffer 1 This starts when the R...

Page 145: ...l of Receive Interrupt to 0 and set enable the interrupt level 1 to 6 to the transfer interrupt In the transfer interrupt program The receiving operation should be done like the above example before setting the next transfer data Example Channel 0 SCLK output Baud rate 9600 bps fc 14 7456 MHz System clock High frequency fc Clock gear 1 fc Prescaler clock fFPH Main routine 7 6 5 4 3 2 1 0 Set the I...

Page 146: ... gear 1 fc Prescaler clock System clock 7 6 5 4 3 2 1 0 PCCR 1 PCFC 1 Set PC0 to function as the TXD0 pin SC0MOD X 0 X 0 1 0 1 Select 7 Bit UART Mode SC0CR X 1 1 X X X 0 0 Add even parity BR0CR 0 0 1 0 0 1 0 1 Set the transfer rate to 2400 bps INTES0 1 1 0 0 Enable the INTTX0 interrupt and set it to Interrupt Level 4 SC0BUF Set data for transmission note X Don t care No change 3 Mode 2 8 Bit UART ...

Page 147: ...ote X Don t care No change 4 Mode 3 9 Bit UART Mode 9 Bit UART Mode is selected by setting SC0MOD0 SM1 SM0 to 11 In this mode parity bit cannot be added In the case of transmission the MSB 9th bit is written to SC0MOD0 TB8 In the case of receiving it is stored in SC0CR RB8 When the buffer is written and read the MSB is read or written first before the rest of the SC0BUF data Wake up function In 9 ...

Page 148: ...ler checks the above select code against its own select code The controller whose code matches clears its WU bit to 0 The master controller transmits data to the specified slave controller whose SC0MOD WU bit is cleared to 0 The MSB bit 8 TB8 is cleared to 0 Data 0 start bit 0 1 2 3 5 4 6 stop 7 bit 8 The other slave controllers whose WU bits remain at 1 ignore the received data because their MSBs...

Page 149: ...1 0 0 1 1 0 1 Enable the INTTX0 interrupt and set it to Interrupt Level 4 Enable the INTRX0 interrupt and set it to Interrupt Level 5 SC0MOD0 1 0 1 0 1 1 1 0 Set fSYS as the transmission clock for 9 Bit UART Mode SC0BUF 0 0 0 0 0 0 0 1 Set the select code for slave controller 1 INTTX0 interrupt SC0MOD0 0 Set TB8 to 0 SC0BUF Set data for transmission Setting the slave controller Main P9CR 0 1 P9FC ...

Page 150: ...outputs 1 to TXD0 pin with either 3 16 or 1 16 times for width of baud rate The pulse width is selected by the SIRCR PLSEL When the transfer data is 1 the modem outputs 0 TXD0 pin 1 0 0 1 1 0 0 Stop 0 Start Transmission data Figure 3 9 25 Modulation example of transfer data 2 Modulation of the receive data When the receive data has the effective high level pulse width software selectable the modem...

Page 151: ... rate generator in SIO0 by setting 01 to SC0MOD0 SC1 0 To use another source TA0TRG fSYS and SCLK0 input are not allowed 2 As the IrDA 1 0 physical layer specification the data transfer speed and infra red pulse width is specified Table 3 9 5 Baud rate and pulse width specifications Baud Rate Modulation Rate Tolerance of rate Pulse Width minimum Pulse Width typical Pulse width maximum 2 4 kbps RZI...

Page 152: ...h 16 k 16 division function can not be used Table 3 9 6 shows Baud rate and pulse width for 16 k 16 division function Table 3 9 7 Baud rate and pulse width for 16 k 16 division function Baud Rate Pulse Width 115 2 kbps 57 6 kbps 38 4 kbps 19 2 kbps 9 6 kbps 2 4 kbps T 3 16 T 1 16 Can be used 16 k 16 division function Can not be used 16 k 16 division function Can not be set to 1 16 pulse width ...

Page 153: ...elect receive pulse width Set effective pulse width for equal or more than 2x x value 1 Can be set 1 to 4 Can not be set 0 15 Select receive pulse width Formula Effective pulse width 2x x value 1 x 1 fFPH 0000 Cannot be set 0001 Equal or more than 4x 100nS to 1110 Equal or more than 30x 100nS 1111 Can not be set Receive operation 0 Disabled 1 Enabled Transmit operation 0 Disabled 1 Enabled Select ...

Page 154: ...P70C P7FC P72F P71F P70F I 2 C Bus Mode 11 11X 11X Clocked Synchronous 8 Bit SIO Mode XX 011 010 X11 X Don t care 3 10 1 Configuration I2 C bus Clock Sysn Control Noise Canceller Shift Register SBI0CR2 SBI0SR SBI0DBR INTSBI Interrupt request φT SBI Control Register 2 SBI Status Register I2 C bus Address Register SBI Data Buffer Register SBI Control Register 1 SBI baud rate Ragister 0 1 SDA SO SI S...

Page 155: ...3 10 4 I2C bus Mode Control and 3 10 7 Clocked synchronous 8 bit SIO Mode Control 3 10 3 The Data Formats in the I 2 C Bus Mode The data formats in the I 2 C bus mode is shown below S a Addressing format b Addressing format with restart c Free data format data transferred from master device to slave device Slave address Data A C K P S S S P P 8 bits 1 to 8 bits R W 1 1 1 or more 1 to 8 bits A C K ...

Page 156: ...1 400 kHz 222 kHz 118 kHz 60 6 kHz 30 8 kHz 15 5 kHz 7 78 kHz reserved System clock fc Clock gear fc 1 fc 16 MHz internal SCL output fscl Hz Software reset state monitor SWRMON read 0 During software reset 1 Not during soft ware reset Acknowledge mode specification 0 Not generate clock pulse for acknowledge signal 1 Generate clock pulse for acknowledge signal Number of bits transferred ACK 0 ACK 1...

Page 157: ...ng mode selection Note 2 00 Port Mode Serial Bus Interface output disabled 01 Clocked Synchronous 8 Bit SIO Mode 10 I 2 C Bus Mode 11 reserved INTSBI interrupt request 0 1 Cancel interrupt request Start Stop generation 0 Generates the stop condition 1 Generates the start condition Transmitter Receiver selection 0 Receiver 1 Transmitter Master Slave selection 0 Slave 1 Master SBI0CR2 0243H Note1 Re...

Page 158: ...nitor 0 0 1 1 Last received bit monitor 0 Last received bit was 0 1 Last received bit was 1 GENERAL CALL detection monitor 0 1 GENERAL CALL detected Slave address match detection monitor 0 1 Slave address match or GENERAL CALL detected Arbitration lost detection monitor 0 1 Arbitration lost INTSBI interrupt request monitor 0 Interrupt requested 1 Interrupt canceled I 2 C bus status monitor 0 Free ...

Page 159: ... 0 Bit symbol DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read Write R received W transfer After Reset Undefined Note When writing transmitted data start from the MSB bit 7 I 2 C Bus Address Register 7 6 5 4 3 2 1 0 bit Symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS Read Write W After Reset 0 0 0 0 0 0 0 0 Function Slave address selection for when device is operating as slave device Address recognition mode specifica...

Page 160: ...Non Acknowledge Mode The TMP91C824F does not generate a clock pulse for the Acknowledge signal when operating in the Master Mode and it does not count a clock pulse as an Acknowledge signal when operating in Slave Mode 2 Number of transfer bits The SBI0CR1 BC2 to BC0 is used to select a number of bits for next transmitting and receiving data Since the BC2 to BC0 is cleared to 000 as a start condit...

Page 161: ...a counter of High level width of an own clock pulse and sets the internal SCL output to the Low level Master A finishes counting Low level width of an own clock pulse at point b and sets the internal SCL output to the High level Since Master B holds the SCL line of the bus at the Low level Master A wait for counting high level width of an own clock pulse After Master B finishes counting low level ...

Page 162: ... condition generation When the SBI0SR BB is 0 8 bit data which are set to SBI0DBR are output on a bus after generating a start condition by writing 1 to the SBI0CR2 MST TRX BB PIN It is necessary to set transmitted data to the data buffer register SBI0DBR and set 1 to ACK beforehand SCL line Start condition A6 Slave address and the direction bit Acknowledge signal 1 SDA line 2 3 4 5 6 7 8 9 A5 A4 ...

Page 163: ...itration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2 C Bus Mode a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data Data on the SDA line is used for I2 C bus arbitration The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus Mast...

Page 164: ...of when TMP91CW12 is a Master Device B D7A D7B D6A D6B 11 Slave address match detection monitor SBI0SR AAS is set to 1 in Slave Mode in Address Recognition Mode i e when I2C0AR ALS 0 when a GENERAL CALL is received or when a slave address matches the value set in I2C0AR When I2C0AR ALS 1 SBI0SR AAS is set to 1 after the first word of data has been received SBI0SR AAS is cleared to 0 when data is w...

Page 165: ...r writing the SBI0DBR In the master mode after the start condition is generated the slave address and the direction bit are set in this register 16 I2 CBUS Address Register I2C0AR I2C0AR SA6 to SA0 is used to set the slave address when the TMP91C824F functions as a slave device The slave address output from the master device is recognized by setting the I2C0AR ALS to 0 The data format is the addre...

Page 166: ...ve address and the direction bit which are set to the SBI0DBR At the 9th clock the SDA line is released and the acknowledge signal is received from the slave device An INTS2 interrupt request occurs at the falling edge of the 9th clock The PIN is cleared to 0 In the Master Mode the SCL pin is pulled down to the Low level while PIN is 0 When an interrupt request occurs the TRX is changed according ...

Page 167: ...ate data transfer When the LRB is 0 the receiver is requests new data When the next transmitted data is 8 bits write the transmitted data to SBI0DBR When the next transmitted data is other than 8 bits set the BC2 to BC0 ACK and write the transmitted data to SBI0DBR After written the data PIN becomes 1 a serial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then...

Page 168: ...ut from Slave D0 Read SBI0DBR New D7 Figure 3 10 15 Example of when BC2 to 0 000 ACK 1 in Receiver Mode In order to terminate the transmission of data to a transmitter clear ACK to 0 before reading data which is 1 word before the last data to be received The last data word does not generate a clock pulse as the Acknowledge signal After the data has been transmitted and an interrupt request has bee...

Page 169: ...it sent from another master is 1 1 0 In Salve Receiver Mode the TMP91C824F receives a slave address for which the value of the direction bit sent from the master is 1 Set the number of bits a word in BC2 to BC0 and write the transmitted data to SBI0DBR 1 0 0 0 In Salve Transmitter Mode a single word of is transmitted Set BC2 to BC0 to the number of bits in a word Check the LRB setting If LRB is se...

Page 170: ...ion when the other device has released the SCL line When SBI0CR2 MST TRX PIN are written 1 and BB is written 0 BB changes to 0 by internal SCL changes to 1 without waiting stop condition To check whether SCL and SDA pin are 1 by sensing their ports is needed to detect bus free condition Internal SCL SDA pin PIN BB read Stop condition 1 MST 1 TRX 0 BB 1 PIN SCL pin Figure 3 10 17 Stop condition gen...

Page 171: ...SBI0SR BB is 0 and SCL terminal level is 1 to check that the TMP91C824F is released Check the LRB until it becomes 1 to check that the SCL line on a bus is not pulled down to the low level by other devices After confirming that a bus stays in a free state generate a start condition with procedure 3 10 6 2 In order to meet setup time when restarting take at least 4 7 μs of waiting time by software ...

Page 172: ...7 n 8 n 9 n 10 1 MHz 500 kHz 250 kHz 125 kHz 62 5 kHz 31 25 kHz 1 625 kHz External mode System clcok fc Clock gear fc 1 fc 16 MHz output to SCK pin fscl Hz Input from SCK terminal Software Reset state monitor SWRMON read 0 Software Reset in progress 1 Software Reset not in progress Transfer mode selection 00 8 Bit Transmit Mode 01 reserved 10 8 Bit Transmit Received Mode 11 8 Bit Received Mode Con...

Page 173: ...0 I 2 C Bus Mode 11 reserved Note Set the SBI0CR1 BC2 to 0 000 before switching to a clocked synchronous 8 bit SIO mode Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 bit Symbol SIOF SEF Read Write R After reset 0 0 Function Serial transfer operation status monitor Shift operation status monitor Shift operation status monitor 0 Shift operation terminated 1 Shift operation in progress Serial ...

Page 174: ...on Allways 0 write IDLE2 0 STOP 1 RUN Operation in IDLE 2 Mode 0 Stop 1 Operate Serial Bus Interface Baud Rate Register 1 7 6 5 4 3 2 1 0 Bit symbol P4EN Read Write R W After Reset 0 Function Internal clock 0 Stop 1 Operate Baud rate clock control 0 Stop 1 Operate SBI0BR0 0244H SBI0BR1 0245H Figure 3 10 22 Registers for the SIO Mode ...

Page 175: ...al clock and holds the next shift operation until reading or writing has been completed SCK pin output SO pin output Write transmitted data 3 1 7 2 8 1 2 6 7 8 1 2 3 c0 a b c Automatic wait function a0 a1 a2 a5 a6 a7 b0 b5 b6 b7 c1 c2 b1 b4 Figure 3 10 23 Automatic wait Function External clock SCK2 to SCK0 111 An external clock input via the SCK pin is used as the serial clock In order to ensure t...

Page 176: ...ing edge shift Data is shifted on the trailing edge of the serial clock on the rising edge of the SCK pin input output bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 7654321 765432 76543 7654 765 76 7 SO pin output 6543210 543210 0 10 210 3210 43210 76543210 SCK pin output Shift register SCK pin SI pin Shift register a Leading edge b Trailing edge Note Don t care bit 0 bit 1 bit 2 bit 3 ...

Page 177: ...a is written automatic wait function is canceled When the external clock is used data should be written to SBI0DBR before new data is shifted The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to SBI0DBR by the interrupt service program When the transmit is started after the SBI0SR SIOF goes 1 output ...

Page 178: ...2 b3 b4 b5 b6 b7 Clear SIOS a Write transmitted data a Internal clock SBI0DBR INTSBI interrupt request SIOS SIOF SEF SCK pin input SO pin b a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Clear SIOS a Write transmitted data b External clock Figure 3 10 26 Transfer Mode STEST1 BIT SEF SBI0SR If SEF 1 then loop JR NZ STEST1 STEST2 BIT 0 P6 If SCK 0 then loop JR Z STEST2 LD SBI0CR1 00000111B SIOS 0 ...

Page 179: ...SBI0DBR before the next serial clock pulse is input If the received data is not read any further data which is to be received is canceled The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when the received data is read Receiving of data ends when SIOS is cleared to 0 by the buffer full inte...

Page 180: ...d data has been read and the next data has been written When an external clock is used since the shift operation is synchronized with the external clock received data is read and transmitted data is written before a new shift operation is executed The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and th...

Page 181: ...rite transmitted data a Read received data d a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 d b c a Read received data c Write transmitted data b Figure 3 10 29 Transmit Received Mode example using internal clock Bit 7 in last transmitted word SCK pin SIOF SO pin bit 6 tSODH Min 4 fFPH s Figure 3 10 30 Transmitted data hold time at end of transmit receive ...

Page 182: ... even though the internal comparator is still enabled Therefore be sure to check that A D converter operations are halted before a HALT instruction is executed INTAD interrupt AN7 P87 AN6 P86 AN5 P85 AN4 P84 AN3 ADTRG P83 AN2 P82 AN1 P81 AN0 P80 Comparator VREFH VREFL Multiplexer Sample and Hold A D mode control register 1 ADMOD1 ADMOD1 ADTRGE ADCH2 to ADCH0 VREFON Scan Repeat Interrupt Busy End S...

Page 183: ...ery conversion 1 every fourth conversion Repeat mode specification 0 Single Conversion 1 Repeat Conversion Mode Scan mode specification 0 Conversion Channel Fixed Mode 1 Conversion Channel Scan Mode A D conversion start 0 Don t care 1 start conversion Always 0 when read A D conversion start 0 Don t care 1 Start A D conversion note Always read as 0 A D scan mode setting 0 A D Conversion Channel Fix...

Page 184: ...anned 000 AN0 AN0 001 AN1 AN0 AN1 010 AN2 AN0 AN1 AN2 011 Note AN3 AN0 AN1 AN2 AN3 100 AN4 AN4 101 AN5 AN4 AN5 110 AN6 AN4 AN5 AN6 111 AN7 AN4 AN5 AN6 AN7 A D conversion start control by external trigger ADTRG input 0 Disabled 1 Enabled IDLE2 control 0 Stopped 1 In operation Control of application of reference voltage to A D converter 0 OFF 1 ON Before starting conversion before writing 1 to ADMOD...

Page 185: ...After Reset Undefined 0 Function stores lower 2 bits of A D conversion result A D Conversion Result flag 1 Conversion result stored A D Conversion Data Upper Register 1 5 7 6 5 4 3 2 1 0 Bit symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R After Reset Undefined Function Stores upper 8 bits of A D conversion result 9 8 7 6 5 4 3 2 1 0 Channel x conversion result 7 6 5 4 3 2 1 0 7...

Page 186: ...fter Reset Undefined 0 Function Stores lower 2 bits of AD conversion result AD Conversion Data Storage flag 1 conversion result stored A D Conversion Result Upper Register 3 7 7 6 5 4 3 2 1 0 Bit symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R After Reset Undefined Function Stores upper 8 bits of A D conversion result 9 8 7 6 5 4 3 2 1 0 Channel x conversion result 7 6 5 4 3 2 ...

Page 187: ...0 ADS to 1 2 Analog input channel selection The analog input channel selection varies depends on the operation mode of the A D converter In Analog Input Channel Fixed Mode A D MOD0 SCAN 0 Setting ADMOD1 ADCH2 to ADCH0 selects one of the input pins AN0 to AN7 as the input channel In Analog Input Channel Scan Mode ADMOD0 SCAN 1 Setting ADMOD1 ADCH2 to ADCH0 selects one of the 8 scan modes Table 3 11...

Page 188: ...Fixed Repeat Conversion Mode Channel Scan Repeat Conversion Mode The ADMOD0 REPET and ADMOD0 SCAN settings in A D Mode Control Register 0 determine the A D mode setting Completion of A D conversion triggers an INTAD A D Conversion End interrupt request Also ADMOD0 EOCF will be set to 1 to indicate that A D conversion has been completed Channel Fixed Single Conversion Mode Setting ADMOD0 REPET and ...

Page 189: ...peat conversion mode i e in cases and write a 0 to ADMOD0 REPET After the current conversion has been completed the repeat conversion mode terminates and ADMOD0 ADBF is cleared to 0 Switching to a halt state IDLE2 Mode with ADMOD1 I2AD cleared to 0 IDLE1 Mode or STOP Mode immediately stops operation of the A D converter even when A D conversion is still in progress In repeat conversion modes i e i...

Page 190: ... hold the results of A D conversion Table 3 11 3 Correspondence Between Analog Input Channels and A D Conversion Result Registers A D Conversion Result Register Analog input channel Port A Conversion modes other than at right Channel fixed repeat conversion mode every 4th conversion AN0 ADREG04H L AN1 ADREG15H L AN2 ADREG26H L AN3 ADREG37H L AN4 ADREG04H L AN5 ADREG15H L AN6 ADREG26H L AN7 ADREG37...

Page 191: ...on Mode Interrupt routine processing example WA ADREG37 Read value of ADREG37L and ADREG37H into 16 bit general purpose register WA WA 6 Shift contents read into WA six times to right and zero fill upper bits 0800H WA Write contents of WA to memory address 0800H This example repeatedly converts the analog input voltages on the three pins AN0 AN1 and AN2 using Channel Scan Repeat Conversion Mode IN...

Page 192: ...function it generates a non maskable interrupt INTWD to notify the CPU Connecting the watch dog timer output to the Reset pin internally forces a reset 3 12 1 Configuration Figure 3 12 1 is a block diagram of he watchdog timer WDT Internal Reset WDMOD WDTP1 to WDTP0 WDMOD WDTE Reset WDT Control register WDCR Q R S Binary Counter 22 Stage 2 21 Internal Reset WDMOD RESCR WDTI interrupt fSYS fFPH 2 S...

Page 193: ...upt and outputs watchdog timer out when an overflow occurs as shown in Figure 3 12 2 0 WDT Interrupt WDT Clear Soft ware Write clear code WDT Counter n Over flow Figure 3 12 2 Normal mode The runaway detection result can also be connected to the Reset pin internally In this case the reset time will be between 22 and 29 states as shown in Figure 3 12 3 Over flow WDT Counter n WDT Interrupt 22 to 29...

Page 194: ... timer to be disabled by runaway However it is possible to return the watch dog timer from the disabled state to the enabled state merely by setting WDTE to 1 Watch dog timer out reset connection RESCR This register is used to connect the output of the watch dog timer with the RESET terminal internally Since WDMOD RESCR is initialized to 0 on Reset a Reset by the watch dog timer will not be perfor...

Page 195: ...atch dog timer Detection Time WDMOD WDTP1 to WDTP0 SYSCR1 System Clcok Selection SYSCK SYSCR1 Gear Value GEAR2 to GEAR0 00 01 10 11 1 fs XXX 2 0 s 8 0 s 32 0 s 128 0 s 000 fc 4 096 ms 16 384 ms 65 536 ms 262 144 ms 001 fc 2 8 192 ms 32 768 ms 131 072 ms 524 288 ms 010 fc 4 16 384 ms 65 536 ms 262 144 ms 1 049 s 011 fc 8 32 768 ms 131 072 ms 524 288 ms 2 097 s 0 fc 100 fc 16 65 536 ms 262 144 ms 1 ...

Page 196: ...6 5 4 3 2 1 0 Bit symbol Read Write W After reset Function B1H WDT disable code 4EH WDT clear code B1H Disable code 4EH Clear code Others Don t care Figure 3 12 5 Watch dog timer control register Disable Clear WDT WDCR 0301H ...

Page 197: ...INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti malfunction program The watch dog timer works immediately after reset The watch dog timer does not operate in IDLE1 or STOP mode as the binary counter continues counting during bus release When BUSAK goes Low When the device is in IDLE2 Mode the operation of WDT depends on the WDMOD I2WDT s...

Page 198: ...e it please manage upper two columns with the system side when handle year column in the Christian era note2 Leap year A leap year is the year which is divisible with 4 but the year which there is exception and is divisible with 100 is not a leap year However the year which is divisible with 400 is a leap year But there is not this product for the correspondence to the above exception Because ther...

Page 199: ...ENA ADJUST ENATMR ENAALM PAGE PAGE register W R W RESTR 0328H DIS1HZ DIS16HZ RSTTMR RSTALM Always Write to 0 Reset register Write only note As for SECR MINR HOURR DAYR MONTHR YEAR of PAGE0 current state is read when read it Table 3 13 2 PAGE 1 Alarm function registers Symbol Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function Read Write SECR 0320H R W MINR 0321H 40 min 20 min 10 min 8...

Page 200: ...Function 0 is read 40 sec column 20 sec Column 10sec Column 8 sec column 4 sec column 2sec column 1sec column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec 0 1 1...

Page 201: ...n column 1min column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0...

Page 202: ... 0 0 0 8 o clock 0 0 1 0 0 1 9 o clock 0 1 0 0 0 0 10 o clock 0 1 1 0 0 1 19 o clock 1 0 0 0 0 0 20 o clock 1 0 0 0 1 1 23 o clock In case of 12 hour clock mode MONTHR MO0 0 of PAGE1 7 6 5 4 3 2 1 0 bit Symbol HO5 HO4 HO3 HO2 HO1 HO0 Read Write R W After reset Undefined Function 0 is read PM AM 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 0 0 0 0 0 0 o clock AM 0 0 0 0 ...

Page 203: ...rday 5 Day column register for PAGE0 1 7 6 5 4 3 2 1 0 bit Symbol DA5 DA4 DA3 DA2 DA1 DA0 Read Write R W After reset Undefined Function 0 is read Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day 1 0 1 0 0 1 29th d...

Page 204: ...1 month 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December 7 Select 24 hour clock or 12 hour clock for PAGE1 only 7 6 5 4 3 2 1 0 bit Symbol MO0 Read Write R W After reset Undefine d Function 0 is read 1 24 hour 0 12 hour MONTHR 0325H MONTHR 032...

Page 205: ... 0 0 0 0 0 1 0 02 year 0 0 0 0 0 0 1 1 03 year 0 0 0 0 0 1 0 0 04 year 0 0 0 0 0 1 0 1 05 year 9 Leap year register for PAGE1 only 7 6 5 4 3 2 1 0 bit Symbol LEAP1 LEAP0 Read Write R W After reset Undefined Function 0 is read 00 leap year 01 one year after leap year 10 two years after leap year 11 three years after leap year 0 0 Current year is leap year 0 1 Present is next year of a leap year 1 0...

Page 206: ... counter is 30 59 min counter is carried and become sec counter to 0 PAGE0 only 11 Reset register setting for PAGE0 1 7 6 5 4 3 2 1 0 bit Symbol DIS1HZ DIS16HZ RSTTMR RSTALM RE3 RE2 RE1 RE0 Read Write W After reset Undefined Function 0 1HZ 0 16HZ 1 TIMER RESET 1 ALARM RESET Please fix to 0 0 1 Reset alarm register 0 1 Timer reset 0 Enable 16Hz clock ALARM output INTRTC 1 Disable 16Hz clock ALARM o...

Page 207: ...wo times with the following way for reading correct data Figure 3 13 2 Flowchart of timer data read As shown in Figure 3 13 2 confirm the data by reading twice and compare them in case reading timer data If it happen to take up a digit the comparing result becomes incorrect Therefore It should be read data again END START PAGER PA0 0 Select PAGE0 Read the timer data 1st Read the timer data 2nd 1 s...

Page 208: ...d a timer of RTC after reading PORT in interrupt routine of ALARM 1 is that carry of RTC timer occurs with rising edge of pulse period of 1 Hz By reading timer during 0 5second after carry happening right data a timer value can be read Read ALARM 1 NO YES NO YES 0 5 second ALARM Internal INTRTC END START Read the timer data ALARM 1 RESTR DIS1HZ 0 RESTR DIS16HZ 1 PAGER ENAALM 0 Enable 1Hz output IN...

Page 209: ...llow the below way Reset for a divider Inside of RTC there is 15 stage divider which generates 1Hz clock from 32 768KHz Carry of a timer is not done for one second when reset this divider So write in data during this interval Figure 3 13 4 Flowchart of data write START PAGER PA0 0 Select PAGE0 RESTR RSTTMR 1 Divider reset Write the timer data note This period is within 0 5 second END ...

Page 210: ...der After becoming timer enable state output the carry signal to timer and revise time and continue operation However timer is late when timer disabling state continues for one second or more During timer disabling pay attention with system power is downed In this case the timer is stopped and time is delayed Figure 3 13 5 Flowchart of timer disable END START Disable the timer Read the timer data ...

Page 211: ... care state which does not set it up is considered to always accord The contents which set it up once cannot be returned to don t care state in independence Initialization of alarm and resetting of alarm register are necessary The following is an example program for outputting an alarm from ALARM pin at noon PM 12 00 every day LD PAGER 09H Alarm disable setting PAGE1 LD RESTR D0H Alarm initialize ...

Page 212: ...n By connecting a loud speaker outside Melody tone can sound easily Alarm generator The Alarm function generates 8 kinds of alarm waveform having a modulation frequency 4096Hz determined by the low speed clock 32 768KHz And this waveform is able to invert by setting a value to a register By connecting a loud speaker outside Alarm tone can sound easily And also 5 kinds of fixed cycle 1Hz 2Hz 64Hz 5...

Page 213: ...lody Generator Edge ditect INTALM0 8KHz INTALM1 512Hz INTALM2 64Hz INTALM3 2Hz INTALM4 1Hz 15bit counter UC1 ALMresistor MELOUT ALMOUT selector MLDALMpin Internal databus Alarm wave form generator MELALMC AC 1 0 Alarm Generator reset 4096Hz invert MELALMC MELALM MELALMC ALMINV ALMINT IALME4 0 INTALMH HALT release 8bit counter UC2 sele cter TA3OUT EMCCR0 TA3MCDE Figure 3 14 1 MLD Block Diagram ...

Page 214: ...lways 0 note2 When setting MELALMC register except FC1 0 during the free run counter is running FC1 0 is kept 01 ALM 0330H MELALMC 0331H MELFL register 7 6 5 4 3 2 1 0 bit Symbol ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 Read Write R W After reset 0 Function Setting melody frequency lower 8bit MELFH register 7 6 5 4 3 2 1 0 bit Symbol MELON ML11 ML10 ML9 ML8 Read Write R W R W After reset 0 0 Function Contr...

Page 215: ...et to 12 bit register MELFH MELFL Followings are setting example and calculation of melody output frequency Formula for calculating of melody waveform frequency fs 32 768 KHz melody output waveform fMLD Hz 32768 2 N 4 setting value for melody N 16384 fMLD 2 notice N 1 4095 001H FFFH 0 is not acceptable Example program In case of outputting La musical scale 440Hz LD MELALMC XXXXX1B select melody wa...

Page 216: ...utput waveform from MLDALM Then alarm pattern have to be set on 8 bit register of ALM Finally 10 be set on MLDALMC AC1 0 register and ALMINV be set as invert By it is setting these values counter start to generate alarm waveform Followings are example program setting value of alarm pattern and waveform of each setting value Setting value of alarm pattern Setting value for ALM register Alarm wavefo...

Page 217: ...L1 pattern Continuous output AL2 pattern 8 times 1sec 1 2 8 31 25ms 1 1sec 1 AL3 pattern once 500ms AL4 pattern Twice 1sec 1 2 62 5ms 1 1sec 1 2 1 AL5 pattern 3 times 1sec 62 5ms 1sec 3 1 AL6 pattern once 62 5ms AL7 pattern Twice 62 5ms 1 2 AL8 pattern once 250ms Modulation frequency 4096Hz ...

Page 218: ...V Vcc 2 7V 0 6 D0 to 15 VIL Vcc 2 7V 0 2Vcc Vcc 2 7V 0 3Vcc P52 to PD7 excep tPB3 VIL1 Vcc 2 7V 0 2Vcc Vcc 2 7V 0 25Vcc RESET NMI PB3 INT0 VIL2 Vcc 2 7V 0 15Vcc Vcc 2 7V 0 3 AM0 1 VIL3 Vcc 2 7V 0 3 Vcc 2 7V 0 2Vcc I n p u t L o w V o l t a g e X1 VIL4 Vcc 2 7V 0 3 0 1Vcc 3 6V Vcc 3 3V 2 4 3 3V Vcc 2 7V 2 0 D0 15 VIH Vcc 2 7V 0 7Vcc Vcc 2 7V 0 7Vcc P52 to PD7 except PB3 VIH1 Vcc 2 7V 0 8Vcc Vcc 2 7...

Page 219: ...0 Programmable Pull Up Resister RKH Vcc 2V 10 200 1000 kΩ NORMAL Note2 14 0 20 0 IDLE2 4 0 6 1 IDLE1 3 6V Vcc 2 7V fc 33MHz 1 2 2 2 mA NORMAL Note2 2 6 3 0 IDLE2 0 7 1 2 IDLE1 Vcc 2V 10 fs 10MHz Typ value Vcc 2 0V 0 2 0 4 mA SLOW Note2 17 5 30 5 IDLE2 7 0 13 5 IDLE1 3 6V Vcc 2 7V fs 32 768kHz 5 0 10 0 μA SLOW Note2 10 5 13 0 IDLE2 4 5 6 5 IDLE1 Vcc 2V 10 fs 32 768kHz Typ Value Vcc 2 0V 3 0 4 5 μA ...

Page 220: ...45 ns 10 tDW D0 to D15 Valid WR Rise 1 5x 35 10 ns 11 tWD WR Rise D0 to D15 Hold x 25 5 ns 12 tAW A0 to A23 Valid WAIT Input 3 5x 60 46 ns 13 tCW RD WR Fall WAIT Hold 2 5x 0 76 ns 14 tAPH A0 to A23 Valid PORT Input 3 5x 89 17 ns 15 tAPH2 A0 to A23 Valid PORT Hold 3 5x 106 ns 16 tAPO A0 to A23 Valid PORT Valid 3 5x 60 166 ns AC Measuring Conditions Output Level High 0 7 Vcc Low 0 3 Vcc CL 50 pF Inp...

Page 221: ... D15 Valid WR Rise 1 5x 70 80 ns 11 tWD WR Rise D0 to D15 Hold x 50 50 ns 12 tAW A0 to A23 Valid WAIT Input 3 5x 120 230 ns 13 tCW RD WR Fall WAIT Hold 2 5x 0 250 ns 14 tAPH A0 to A23 Valid PORT Input 3 5x 50 300 ns 15 tAPH2 A0 to A23 Valid PORT Hold 3 5x 350 ns 16 tAPO A0 to A23 Valid PORT Valid 3 5x 60 410 ns AC Measuring Conditions Output Level High 0 7 V Low 0 3 V CL 50 pF Input Level High 0 9...

Page 222: ...TMP91C824 91C824 219 1 Read Cycle tHR fFPH EA24 25 A23 0 W R Port Input RD D0 15 tFPH tAW tAPH tAD tAC tRR tCAR D0 15 tCW tAPH2 CSn WAIT tRD ...

Page 223: ...TMP91C824 91C824 220 2 Write Cycle D0 15 tWD tAPO tWW tDW fFPH EA24 25 A23 0 W R Port Output D0 15 WAIT HWR WR CSn tCAW ...

Page 224: ...CC 2 V 10 VSS Vss Vss VAIN Analog Input Voltage Range VREFL VREFH V VCC 3 V 10 0 94 1 20 Analog Current for Analog Reference Voltage VREFON 1 VCC 2 V 10 0 65 0 90 mA IREF VREFL 0V VREFON 0 VCC 1 8 V to 3 3 V 0 02 5 0 µA VCC 3 V 10 1 0 4 0 Error not including quantizing errors VCC 2 V 10 1 0 4 0 LSB note1 1 LSB VREFH VREFL 1024 V note2 The operation above is guaranteed for fFPH 4 MHz note3 The valu...

Page 225: ...ode Variable 10 MHz 27 MHz Symbol Parameter Min Max Min Max Min Max Unit TSCY SCLK Period 16X 8192X 1 6 819 0 59 303 µs TOSS Output Data SCLK Rising Falling Edge tSCY 2 40 760 256 ns TOHS SCLK Rising Falling Edge Output Data Hold tSCY 2 40 760 256 ns THSR SCLK Rising Falling Edge Input Data Hold 0 0 0 ns TSRD SCLK Rising Falling Edge Valid Data Input tSCY 1X 180 1320 375 ns TRDS Valid Data Input S...

Page 226: ...0 900 396 ns tVCKL Clock Low Level Width 4X 40 440 188 ns tVCKH Clock High Level Width 4X 40 440 188 ns 4 7 Interrupt Capture 1 NMI INT0 to INT3 Interrupts Variable 10 MHz 27 MHz Symbol Parameter Min Max Min Max Min Max Unit tINTAL NMI INT0 to INT3 Low level width 4X 40 440 188 ns tINTAH NMI INT0 to INT3 High level width 4X 40 440 188 ns ...

Page 227: ... Off to BUSAK Low 0 80 0 80 0 80 ns tBAA BUSAK High to Output Buffer On 0 80 0 80 0 80 ns Note 1 Even if the BUSRQ Signal foes Low the bus will not be released while the WAIT signal is Low The bus will only be released when BUSRQ goes Low while WAIT is High Note 2 This line shows only that the output buffer is in the off state It does not indicate that the signal level is fixed Just after the bus ...

Page 228: ...is sum of external loads C1 and C2 and floating loads of actual assemble board There is a possibility of miss operating using C1 and C2 value in below table When designing board it should design minimum length pattern around oscillator And we recommend that oscillator evaluation try on your actual using board 1 Connection example X1 C1 C2 X2 Rd High frequency oscillator XT1 C1 C2 XT2 Rd Low freque...

Page 229: ...Oscillator C1 pF C2 pF Rf Ω Rd Ω Voltage of Power V Tc 2 00M CSTLS2M00G56 B0 47 47 Open 0 2 50M CSTLS2M50G56 B0 47 47 Open 0 10 00M CSTS1000MG03 CSTLS10M0G53 B0 15 15 Open 0 CSA12 5MTZ093 CSALA12M5T55093 B0 30 30 Open 0 TMP91C824 12 50M CST12 0MTW093 CSTLA12M5T55093 B0 30 30 Open 0 1 8 to 2 2 40 to 85 Parameter of elements Running Condition MCU Oscillation Frequency MHZ Item of Oscillator C1 pF C2...

Page 230: ...marks Table layout Note Prohibit RMW in the table means that you cannot use RMW instructions on these register Example When setting bit0 only of the registerP0CR the instruction SET 0 0002G cannot be used The LD transfer instruction must be used to write all eight bits Read Write R W Both read and write are possible R Only read is possible W Only write is possible W Both read and write are possibl...

Page 231: ...H 2H DMA2V 2H INTE3ALM4 3H 3H DMA3V 3H INTEALM01 4H 4H 4H INTEALM23 5H 5H 5H INTETA01 6H 6H 6H INTETA23 7H 7H 7H INTERTC 8H 8H INTCLR 8H INTES0 9H 9H DMAR 9H INTES1 AH AH DMAB AH INTES2 BH BH BH INTETC01 CH CH IIMC CH INTETC23 DH PZ DH DH INTEP01 EH PZCR EH EH FH PZFC FH FH 4 CS WAIT 5 6 CGEAR DFM Address Name Address Name 00C0H B0CS 00E0H SYSCR0 1H B1CS 1H SYSCR1 2H B2CS 2H SYSCR2 3H B3CS 3H SYSC...

Page 232: ...I2C0AR 3H BR0CR 3H SBI0CR2 SBI0SR 4H BR0ADD 4H SBI0BR0 5H SCMOD1 5H SBI0BR1 6H 6H 7H SIRCR 7H 8H SC1BUF 8H 9H SC1CR 9H AH SC1MOD0 AH BH BR1CR BH CH BR1ADD CH DH SC1MOD1 DH EH EH FH FH 10 10bit ADC Address Name Address Name 02A0H ADREG04L 02B0H ADMOD0 1H ADREG04H 1H ADMOD1 2H ADREG15L 2H 3H ADREG15H 3H 4H ADREG26L 4H 5H ADREG26H 5H 6H ADREG37L 6H 7H ADREG37H 7H 8H 8H 9H 9H AH AH BH BH CH CH DH DH E...

Page 233: ...6H 6H YEWRR 7H 7H PAGER 8H 8H RESTR 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH 13 MLD 13 MMU Address Name Address Name 0330H ALM 0350H LOCAL0 1H MELALMC 1H LOCAL1 2H MELFL 2H LOCAL2 3H MELFH 3H LOCAL3 4H ALMINT 4H 5H 5H 6H 6H 7H 7H 8H 8H 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH Note Do not access to the unnamed addresses i e addresses to which no register has been allocated ...

Page 234: ... Mode P56 P55 P54 R W 1 P5 PORT5 0DH Input Mode Pull Up P67 P66 P65 P64 P63 P62 P61 P60 R W P6 PORT6 12H 1 1 1 1 1 0 1 1 P72 P71 P70 R W 1 1 1 P7 PORT7 13H Input Mode P86 P85 P84 P83 P82 P81 P80 R P8 PORT8 18H Input Mode PB6 PB5 PB4 PB3 PB2 PB1 PB0 R W 1 1 1 1 1 1 1 PB PORTB 22H Input Mode PC5 PC4 PC3 PC2 PC1 PC0 R W 1 1 1 1 1 1 PC PORTC 23H Input Mode PD7 PD6 PD5 R W PD PORTD 29H 1 1 1 PZ3 PZ2 RD...

Page 235: ... PORT 1 BUSRQ P65F P64F P63F P62F P61F P60F W 0 0 0 0 0 0 P6FC PORT6 Function 15H Prohibit RWM Always write 0 0 PORT 1 EA25 0 PORT 1 EA24 0 PORT 1 CS3 0 PORT 1 CS2 0 PORT 1 CS1 0 PORT 1 CS0 P67F2 P66F2 P65F2 P64F2 P62F2 W W 0 0 P6FC2 PORT6 Function2 1BH Prohibit RWM 0 P67F 1 CS2E 0 P66F 1 CS2D 0 P65F 1 CS2C 0 P64F 1 CS2B Always write 0 0 P62F 1 CS2A Always write 0 P72C P71C P70C W 0 0 0 P7CR PORT7...

Page 236: ...0 PORT 1 TA3OUT 0 PORT 1 TA1OUT PC5C PC4C PC3C PC2C PC1C PC0C W 0 0 0 0 0 0 PCCR PORTC Control 26H Prohibit RWM 0 IN 1 OUT PC5F PC3F PC2F PC0F W W W W 0 0 0 0 PCFC PORTC Function 27H Prohibit RWM 0 PORT 1 SCLK1 0 PORT 1 TXD1 0 PORT 1 SCLK0 0 PORT 1 TXD0 ODEPC3 ODEPC0 W W 0 0 PCODE PORTC Open Drain 28H Prohibit RWM 0 CMOS 1 Open Drain 0 CMOS 1 Open Drain PD7F PD6F PD5F W W W 0 0 0 PDFC PORTD Functi...

Page 237: ...2 IA0M1 IA0M0 R R W R R W 0 0 0 0 0 0 0 0 INTE A LM01 Interrupt Enable ALM0 1 93H 1 INTALM1 Interrupt level 1 INTALM0 Interrupt level INTALM3 INTALM2 IA3C IA3M2 IA3M1 IA3M0 IA2C IA2M2 IA2M1 IA2M0 R R W R R W 0 0 0 0 0 0 0 0 INTE A LM23 Interrupt Enable ALM2 3 94H 1 INTALM3 Interrupt level 1 INTALM2 Interrupt level INTTA1 TMRA1 INTTA0 TMRA0 ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0 R R ...

Page 238: ...errupt Enable Serial 1 99H 1 INTTX1 Interrupt level 1 INTRX1 Interrupt level INTS2 IS2C IS2M2 IS2M1 IS2M0 R R W 0 0 0 0 INTES2 Interrupt Enable Serial 2 LCD 9AH 1 INTS2 Interrupt level INTTC1 INTTC0 ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 R R W R R W INTETC 01 Interrupt Enable TC0 1 9BH 0 0 0 0 0 0 0 0 INTTC3 ITC2M0 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R R W R R W IN...

Page 239: ...tart vector CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0 W INTCLR Interrupt Clear Control 88H Prohibit RMW Clears interrupt request flag by writing to DMAstart vector DMAR3 DMAR2 DMAR1 DMAR0 R W R W R W R W 0 0 0 0 DMAR DMA Software Request Register 89H 1 DMA request in software DMAB3 DMAB2 DMAB1 DMAB0 R W R W R W R W 0 0 0 0 DMAB DMA Burst Request Register 8AH 1 DMA request on Burst Mode I3EDGE I2EDGE I1E...

Page 240: ... 000 2WAIT 100 Reserved 001 1WAIT 101 3WAIT 010 1 NWAIT 110 4WAIT 011 0WAIT 111 8WAIT B3E B30M1 B30M0 B3BUS B3W2 B3W1 B3W0 W W W W W W W 0 0 0 0 0 0 0 B3CS Block 3 CS WAIT control Register C3H Prohibit RMW 0 DIS 1 EN 00 ROM SRAM 01 10 Reserved 11 Data bus width 0 16 bit 1 8 bit 000 2WAIT 100 Reserved 001 1WAIT 101 3WAIT 010 1 NWAIT 110 4WAIT 011 0WAIT 111 8WAIT BEXBUS BEXW2 BEXW1 BEXW0 W W W W 0 0...

Page 241: ... A23 to A16 V22 V21 V20 V19 V18 V17 V16 V15 R W 1 1 1 1 1 1 1 1 MAMR2 Memory Address Mask Reg2 CDH CS0 area size 0 enable to address comparison S23 S22 S21 S20 S19 S18 S17 S16 R W 1 1 1 1 1 1 1 1 MSAR3 Memory Start Address Reg3 CEH Start address A23 to A16 V22 V21 V20 V19 V18 V17 V16 V15 R W 1 1 1 1 1 1 1 1 MAMR3 Memory Address Mask Reg3 CFH CS0 area size 0 enable to address comparison ...

Page 242: ...timer 0 write Don t care 1 write start timer 0 read end warm up 1 read not end warm up Select prescaler clock 00 fFPH 01 reserved 10 fc 16 11 reserved SYSCK GEAR2 GEAR1 GEAR0 R W 0 1 0 0 SYSCR1 System Clock Control Register 1 E1H System clock selection 0 fc 1 fs Note 2 High frequency gear value selection fc 000 fc 001 fc 2 010 fc 4 011 fc 8 100 fc 16 101 reserved 110 reserved 111 reserved SCOSEL W...

Page 243: ... DFLAG PFLAG R W R W R W R W R W R W 0 0 0 0 0 0 CS1A Write operation flag CS2B 2G Write operation flag CS2A Write operation flag EMCCR3 EMC Control Register 3 E6H CS1A areadetect enable 0 disable 1 enable CS2B 2G areadetect Enable 0 disable 1 enable CS2A areadetect enable 0 disable 1 enable When reading When writing 0 not written 0 clear flag 1 written 6 DFM clock doubler Symbol Name Address 7 6 ...

Page 244: ...rohibit RMW 00 Invert TA1FF 01 Set TA1FF 10 Clear TA1FF 11 Don t care 1 TA1FF Invert Enable 0 TMRA0 1 TMRA1 inversion 7 2 TMRA23 Symbol Name Address 7 6 5 4 3 2 1 0 TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN R W R W R W R W R W 0 0 0 0 0 TA23 R UN Timer RUN 108H Double Buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 8 Bit Timer Run Stop control 0 Stop Clear 1 Run count up W TA2REG 8 Bit Timer Register ...

Page 245: ...t 00 TA0TRG 01 baud rate generator 10 internal clock fSYS 11 external clock SCLK0 BR0ADD BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R W 0 0 0 0 0 0 0 BR0CR Baud Rate Control 203H Always write 0 1 16 K 16 divided Enable 00 φT0 01 φT2 10 φT8 11 φT32 Set the dividiing value 0 to F BR0K3 BR0K2 BR0K1 BR0K0 R W 0 0 0 0 BR0 AD D Serial Channel 0 K setting Reg 204H Baud Rate0 K 1 to F I2S0 FDPX0 R W R W 0 0 SC...

Page 246: ...1 SM0 SC1 SC0 R W 0 0 0 0 0 0 0 0 SC1 MOD0 Serial Channel 1 Mode 20AH Transmission data bit 8 1 CTS Enable 1 Receive Enable 1 Wake up Enable 00 I O Interface 01 UART 7 bit 10 UART 8 bit 11 UART 9 bit 00 TA0TRG 01 baud rate generater 10 internal clock fSYS 11 external clockSCLK1 BR1ADD BR1CK1 BR1CK BR1S3 BR1S2 BR1S1 BR1S0 R W 0 0 0 0 0 0 0 0 BR1CR Baud Rate Control 20BH Always write 0 1 16 K 16 div...

Page 247: ...ffer Register 241H Prohibit RMW Undefined SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS W W W W R W R W R W R W 0 0 0 0 0 0 0 0 I2C0AR I2CBUS Address Register 242H Prohibit RMW Setting slave address Address recognition 0 Enable 1 Disable MST TRX BB PIN AL SBIM1 AAS SBIM0 AD0 SWRST LRB SWRST0 R W R W R W R W R W R W R W R W 0 0 0 1 0 0 0 0 243H I2 C bus Mode Prohibit RMW 0 Slave 1 Master 0 receiver 1 transmit Bu...

Page 248: ...6 AN4 AN5 AN6 111 AN7 AN4 AN5 AN6 AN7 ADR01 ADR00 ADR0RF R R AD REG04L AD Result Reg 0 4 low 2A0H Undefined 0 ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R AD REG04H AD Result Reg 0 4 high 2A1H Undefined ADR11 ADR10 ADR1RF R R AD REG15L AD Result Reg 1 5 low 2A2H Undefined 0 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 R AD REG15H AD Result Reg 1 5 high 2A3H Undefined ADR21 ADR20 ADR2RF R R...

Page 249: ...DTP1 WDTP0 I2WDT RESCR R W R W R W R W R W R W 1 0 0 0 0 0 WDMOD WDT MODE Reg 300H 1 WDT Enable 00 215 fsys 01 217 fsys 10 219 fsys 11 221 fsys IDLE2 0 Abort 1 Operate 1 RESET connect internally WDT out to Reset pin Always write 0 W WDCR WD Control 301H B1H WDT Disable 4EH WDT Clear ...

Page 250: ... W Undefined DATER Date Reg 324H 0 0 20 day 10 day 8 day 4 day 2 day 1 day MO4 MO3 MO2 MO1 MO0 R W 325H Undefined PAGE0 0 0 0 10 month 8 month 4 month 2 month 1 month MONTHR Month Reg PAGE1 0 Indicator for 12 hours 1 Indicator for 24 hours YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 R W 326H Undefined PAGE0 80 year 40 year 20 year 10 year 8 year 4 year 2 year 1 year YEARR Year Reg PAGE1 Leap year setting INTR...

Page 251: ...10 Clear 11 Clear Start Alarm Frequency Invert 1 Invert Always write 0 Output Frequency 0 Alarm 1 Melody ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 R W 0 MELFL Melody Frequency L Reg 332H Melody Frequency set low 8bit MELON ML11 ML10 ML9 ML8 R W R W 0 0 MELFH Melody Frequency H Reg 333H Melody counter Control 0 Stop and Clear 1 Start Melody Frequency set high 4bit IALM4E IALM3E IALM2E IALM1E IALM0E R W 0 ALM...

Page 252: ...AL0 area BANK set L1E L1EA23 L1EA22 L1EA21 R W R W 0 0 LOCAL 1 LOCAL1 Control Reg 351H 0 Disable 1 Enable LOCAL1 area ANK set L2E L2EA23 L2EA22 L2EA21 R W R W 0 0 LOCAL 2 LOCAL2 Control Reg 352H 0 Disable 1 Enable LOCAL2 area BANK set L3E L3EA26 L3EA25 L3EA24 L3EA23 L3EA22 R W R W 0 0 LOCAL 3 LOCAL3 Control Reg 353H 0 Disable 1 Enable LOCAL3 area BANK set ...

Page 253: ...write instructions on the TLCS 900 Exchange instruction EX mem R Arithmetic operations ADD mem R ADC mem R SUB mem R SBC mem R INC 3 mem DEC 3 mem Logic operations AND mem R OR mem R XOR mem R Bit manipulation operations STCF 3 A mem RES 3 mem SET 3 mem CHG 3 mem TSET 3 mem Rotate and shift operations RLC mem RRC mem RL mem RR mem SLA mem SRA mem SLL mem SRL mem RLD mem RRD mem 3 fc fs fFPH fSYS a...

Page 254: ...er is not to be used disable it h AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption When STOP Mode is used disable the resistor using the program before the HALT instruction is executed i CPU micro DMA Only the LDC cr r and LDC r cr instructions can be used to access the control registers in the CPU e g the Transfer Source A...

Page 255: ...FP Flat Package PACKAGE NAME P LQFP100 P 1414 0 5D 75 76 51 50 26 100 25 1 14 0 0 1 16 0 0 2 1 0TYP 1 0TYP 14 0 0 1 16 0 0 2 0 22 0 05 0 04 75 0 5 0 08 M 15 0 0 2 1 6MAX 1 4 0 05 0 1 0 05 0 08 0 45 0 75 0 10 0 145 0 055 0 045 Item mm ...

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