Toshiba T-Series T1200 User Manual Download Page 5

Page: 5 / 213

Summary of Contents for T-Series T1200

Page 1: ...act size and internal battery pack which is removal Hardware of the T1200 most of IC chips are C MOS type so that the power consumption is very little and Gate Array chips are applied so that it is very compact and light weight The Tl200 is composed of as follows System PCB Printed curcuit board 3 5 inch floppy disk drive 3 5 inch hard disk drive LCD Liquid crystal display Keyboard Intelligent pow...

Page 2: ...apart from those ordinary power serving functions this unit contains a so called one chip microcomputer and it controls the whole system PCB FOO HOD and HOC The built in modem expands the capabilities of your system The built in modem enables the system to communicate with an asynchronous communications device through a telephone line The modem can operate communications at either low 300 bps or h...

Page 3: ...xpanded memory BIOS ROM Video RAM 640 kbytes 384 kbytes 32 kbytes 16 kbytes o System support elements Direct memory access DMA 82C37 Timer 82C53 Programmable interrupt controller PIC 82C59 o Floppy disk controller FDC 8565 o Keyboard controller KBC 80C49 o Acynchronous communication element ACE 8570 o Gate array Bus driver Bus controller EXP MEM controller Display controller 1 3 ...

Page 4: ...umper straps The system PCB has five jumper straps PJ17 PJ18 PJ19 PJ20 and PJ2l The following figure shows location of the jumper straps I PJ21 PJ18 PJ19 PJ20 I11III PJ17 FIGURE 1 2 Jumper Straps Location 1 4 ...

Page 5: ...ins Description D F F type PJ17 1 2 F H type PJ18 D 3 Normal PJ18 PJ19 1 2 PJ19 PJ18 1 G When connect an ICE to the co processor socket PJ19D D No co processor PJ20 1 2 When connect a co processor to the co processor socket D Display a normal font PJ21 1 2 Displays a North Europian Denmark font 1 5 ...

Page 6: ...ing table FIGURE 1 3 3 5 inch FDD T BLE 1 2 3 5 inch Floppy Disk Drive Specifications Item Specifications Storage Capacity kilobytes 1000 unformatted 720 formatted Number of Heads 2 Number of Track per Side 80 Track to Track Access milliseconds 6 Head Settling Time milliseconds 1S Track Density tracks per second 135 Motor Start up Time milliseconds 500 Data Transfer Rate kilobits per second 250 Ro...

Page 7: ...fications are as following table FIGURE 1 4 3 5 inch Hard Disk Drive TABLE 1 3 3 5 inch Hard Disk Drive Specifications Item Specifications Storage Capacity megabytes 25 3 unformatted 21 4 formatted Number of Heads 2 Number of Track per Side 615 Access Time milliseconds minimum 24 average 78 maximum 130 Data Transfer Rate megabits per second 7 5 Rotational Speed revolutions per minute 2597 Recordin...

Page 8: ... HOC can interface the HOD to the system PCB The specifications are as following table FIGURE 1 5 Hard Disk Control PCB TABLE 1 4 Hard Disk Control PCB Specifications Item Specifications Encoding method 2 7 RLL Run Length Limited Data Transfer Rate megabits per second maximum 7 S Write Precompensation time nanoseconds 12 Sectorina Soft 1 8 ...

Page 9: ...onsist of 48 standard keys 10 function keys 10 cursor keys 13 functional keypads and Fn key The keyboard is just a key matrix built up by the above keys The keyboard is connected to the keyboard controller on the system PCB through a 22 pin flat cable FIGURE 1 6 Keyboard 1 9 ...

Page 10: ...er inputs and a contrast control input from the system PCB All timing pulses and data signals are TTL level compatible Specifications are as following table FIGURE 1 7 Liquid Crystal Display TABLE 1 5 Liquid Crystal Display Spesifications Item Specification Outline Dimension mm 275 0 W x 126 0 H x 15 8 D Number of Dots 640 x 200 dots Number of characters 80 x 25 2000 Characters 8 x 8 dot format al...

Page 11: ...off control of the system unit 4 Self diagnosis of the power supply 5 Pays a role of interface with the CPU Communication control Reset signal generation Low battery signal generation 6 Display control AC adapter connection Battery recharge Abnormal power supply Output rating is as following table FIGURE 1 8 Power Suplly PCB TABLE 1 6 Power Supply PCB Output Rating FUNCTION DC VOLTAGE REGULATION T...

Page 12: ...he BELL 103 212 communication T e specifications are as following table FIGURE 1 9 Built in Modem TABLE 1 7 Built in Modem Specifications Item Specification Data Format Low Speed 300 BPS 7 or 8 bits 1 or 2 stop bits odd even or no parity High Speed 1200 BPS 7 bits no parity 2 stop bits 7 bits e o parity 1stop bit 8 bits no parity 1stop bit Dialing Capability Tone Diall Pulse Dial Audio Monitor Spe...

Page 13: ...odem 1200 s configuration switch 1 UP This is the setting required for most applications This setting enables data terminal PJS ready DTR r Joining pins 2 and 3 is the same as setting a 1 12 3 1 Smartmodem 1200 s configuration switch 1 1 1 DOWN This setting sets DTR alwayus TRUE Joining pins 1 and 2 is the same as setting a D Smartmodem 1200 s configuration switch 6 UP 3 This setting enables the c...

Page 14: ... Diagnostics disk 2 Flatbladed screwdriver 3 Work disk for FDD testing 4 Cleaning disk kit for FDD testing 5 Multimeter 6 Printer port LED The problem isolation flowchart described in part 2 2 can be used to determine the necessary isolation procedures to be followed when there is a problem with the T1200 2 2 PROBLEM ISOLA l IOR BAR r This flowchart is used as a guide for determining which FRU is ...

Page 15: ...3 Yes Perfor system PCB problem isolation procedures in part 2 4 No Perform LCD problem isolation __ procedures 1n part 2 7 Perform syste PCB proble No _ holat1on procedures in part 2 4 Perform system PCB proble _N_o_ holat1on procedures in part 2 4 FIGURE 2 1 Problem Isolation Flowchart 2 2 ...

Page 16: ... the relevant Yes problem isolation procedures as indicated below 1 If an error is generated on the system test memory test display test and real time test go to system PCB isolation procedures in part 2 4 2 If an error is generated on the keyboard test go to keyboard isolation procedures in part 2 8 3 If an error is generated on the floppy disk test go to FDD isolation procedures in part 2 5 2 3 ...

Page 17: ...ply PCB is defective or not The procedures below are outlined in the following pages They should be performed in the order indicated PROCEDURE 1 Battery Check PROCEDURE 2 Power Supply Indicator Check PROCEDURE 3 Connector Check PROCEDURE 4 Output Voltage Check PROCEDURE 5 Power Supply PCB Replacement 2 4 ...

Page 18: ...e ac adapter 3 Turn the POWER switch on If the Low Battery indicator lights plug the ac adapter into the DC IN l2V jack If the indicator then goes out the battery is normal and you should go to PROCEDURE 3 if it remains lit go to PROCEDURE 2 FIGURE 2 2 Battery Check 2 5 ...

Page 19: ...s flowing the ac adapter is normal GREEN CONTINUOUSLY LIT Either the main disconnected or current flow has stopped complete the ac adapter is normal battery charging is is RED BLINKING Current is not being supplied by the ac adapter the adapter must be replaced If the indicator still blinks after replacing the ac adapter replace the power supply PCB See part 4 8 4 If the indicator does not light t...

Page 20: ...move the top cover assembly Refer to part 4 2 3 If the three power supply PCB connectors PJ 2 3 and 4 and the two system PCB connectors PJ 9 and 12 are connected properly go to PROCEDURE 4 if they are not connected properly reconnect them FIGURE 2 4 Power Supply and System PCB Connectors 2 7 ...

Page 21: ...llowing table 6 If the voltages conform to the values given in the table the power supply PCB is normal System PCB is probably defective go to system PCB isolation procedures in part 2 4 7 If the voltages do not conform to those given in the table go to PROCEDURE 6 TABLE 2 1 Power Supply PCB Output Voltages CONNECTOR PIN NUMBER VOLTAGE Vdc lead lead Normal Min Max PJ 2 1 2 5 4 75 5 25 PJ 4 6 3 7 1...

Page 22: ...apter from the DC IN l2V jack 3 Replace the power supply PCB Refer to part 4 8 4 If normal operation is restored after replacing the PCB the previous PCB was defective 5 If normal operation is not restored another FRU is probably defective The defective unit must be isolated and replaced 2 9 ...

Page 23: ... following pages They should be performed in the order indicated PROCEDURE 1 Message Check PROCEDURE 2 Printer Port LED Check PROCEDURE 3 Jumper Straps Check PROCEDURE 4 Test Program Execution PROCEDURE 5 System PCB Replacement NO l E Before carrying out any of these procedures make sure that there is not a floppy disk in the FDD and the HOD switch is off 2 10 ...

Page 24: ...n ready 2 If the above message is not displayed check to see if any of the following messages are displayed TABLE 2 2 Error Messages KEYBOARD ERROR FDD ERROR OPTION ERROR RTC ERROR DISK 0 FAILURE DISK CONTROLLER FAILURE 3 If any of the above messages are displayed go to PROCEDURE 3 4 If none of the above messages are displayed go to PROCEDURE 2 2 11 ...

Page 25: ... as a hexadecimal value from left to right 5 If the final LED status matches any of the error status and OK status values in the following table go to PROCEDURE 5 6 If the final LED status is PBB go to PROCEDURE 3 and continue TABLE 2 3 Printer Port LED Error Status and OK Status Test Name Error Status OK Status BIOS ROM test 01H 11H Timer 82C53 test 02H 03H 12H DMAC 82C37 test 04H 05H 14H RAM PJW...

Page 26: ... cover assembly Refer to part 4 2 3 Confirm that the jumper straps status is normal Refer to part 1 2 1 4 If the jumper strap status is normal go to PROCEDURE 4 5 If the jumper strap status is not normal set them correctrv I PJ21 PJ1S PJ19 PJ20 PJ17 FIGURE 2 5 Jumper Straps 2 13 ...

Page 27: ...loppy disk test 6 Real time test 2 If an error is generated on the system test memory test display test and real time test go to system PCB isolation procedures in part 2 4 3 If an error is generated on the floppy disk test go to FDD isolation procedures in part 2 5 4 If an error is generated on the keyboard test go to keyboard isolation procedures in part 2 7 2 14 ...

Page 28: ...the system PCB Refer to part 4 13 2 If normal operation is restored after replacing the PCB the previous PCB was defective 3 If normal operation is not restored another FRU is probably defective The defective unit must be isolated and replaced 2 15 ...

Page 29: ...edures below are outlined in the following pages They should be performed in the order indicated PROCEDURE 1 Test and Diagnostic Program Loading Check PROCEDURE 2 Message Check PROCEDURE 3 Head Cleaning PROCEDURE 4 FDD Test Execution PROCEDURE 5 FDD Connector Check PROCEDURE 6 New FDD connection ROTE Make sure that the HOD switch is off 2 16 ...

Page 30: ...urn the POWER switch off 2 Insert the diagnostics disk into the FDD 3 Turn the POWER switch on 4 If loading occurs normally go to PROCEDURE 3 See PART 3 to determine if loading has occurred normally 5 If loading has not occurred normally go to PROCEDURE 2 2 17 ...

Page 31: ... Non System disk or disk error Replace and press any key when ready 2 If ei ther of the above messages is displayed the contents of the floppy disk are damaged or some other disk than the diagnostics disk has been inserted into the FDD Change the diagnostics disk If loading then occurs go to PROCEDURE 4 if loading does not occur go to PROCEDURE 3 3 If neither of the above messages appears go to PR...

Page 32: ...e cleaning disk to the FOO 3 Turn the POWER switch on then will clean the head od the FOD 4 Remove the cleaning disk from the FOD 5 If normal operation is restored after cleaning the head go to PROCEDURE 4 6 If normal operation is not restored go to PROCEDURE 5 2 19 ...

Page 33: ...the following table Follow the directions provided in the table 3 If no error is generated the FDD is normal TABLE 2 4 FDD Error Statuses CODE STATUS 01 Bad Command 02 Address Mark Not Found 03 Write Protected 04 Record Not Found 06 Media removed on dual attach card 08 DMA Overrun Error 09 DMA Boundary Error 10 CRC Error 20 FDC Error 40 SEEK ERROR 60 FDD not drive 80 Time Out Error Not Ready EE Wr...

Page 34: ...e DC IN 12V jack 2 Remove the top cover assembly Refer to part 4 2 3 If the FDD cable is connected to the system PCB securely and if the A and B drives are connected correctly go to PROCEDURE 6 4 If the above connections are not secure reconnect them FDD Conector FIGURE 2 6 FDD Connector Check 2 21 ...

Page 35: ...Connect the new FOO to the FOO connector then other connectors too 4 Turn the POWER switch on 5 If normal operation is restored after connect the new FOO the previous FOO was defective Assemble the system 6 If normal operation is not restored system PCB is probably defective Refer to part 2 4 2 22 ...

Page 36: ... procedures below are outlined in the following pages They should be performed in the order indicated PROCEDURE 1 HDD Indicator Check PROCEDURE 2 Format Execution PROCEDURE 3 Hard Disk Test Execution PROCEDURE 4 Connector Check PROCEDURE 5 Jumper Strap Check PROCEDURE 6 New HDD Connection Rote Make sure that the HDD switch is on 2 23 ...

Page 37: ...firm that the HOD switch turn on then turn the POWER switch on 4 If the HOD indicator C Lower blinks briefly and goes out go to PROCEDURE 2 if it continues blinking go to PROCEDURE 2 5 If the indicator does not light at all go to PROCEDURE 4 CJ CJ_cCJ _ CJ _ _ CIIr L Disk in Use II FIGURE 2 7 HOD Indicator Check 2 24 ...

Page 38: ...S BACKUP command See the MS DOS manual for details 1 Remove the diagnostics disk and then insert the ME DOS system disk to the FDD 2 To set the partition of the hard disk enter the FDISK command See the MS DOS manual for details 3 To format the hard disk enter the FORMAT command See the MS DOS manual for details 4 If normal operation is restored the HOD is normal 5 If normal operation is not resto...

Page 39: ...uring the hard disk test an error code and status will be displayed as indicated in the following table Go to PROCEDURE 3 4 If no error is generated the HDD is normal Enter the MS DOS FDISK command which will set the partition Then enter the MS DOS FORMAT command See the MS DOS manual for details TABLE 2 5 HDD Error Statuses CODE STATUS 01 Bad command error 02 Bad address mark 04 Record not found ...

Page 40: ...onnect the ac adapter from the DC IN l2V jack 3 Remove the top cover assembly Refer to part 4 2 4 If the HOD HOC and system PCB are connected securely go to PROCEDURE 5 5 If they are not connected securely reconnect them FIGURE 2 8 HOC and HOD Connector Check 2 27 ...

Page 41: ...k control PCB is as following status Refer to part 1 2 1 and 1 5 1 PJ 17 system PCB Open PJ 9 hard disk control PCB Short 2 If the jumper strap is above status go to PROCEDURE 6 3 If the jumper strap is not above status set the jumper strap correctly Pl9 Hard Disk Control PCB PUI put System PCB FIGURE 2 9 Jumper Straps 2 28 ...

Page 42: ... DC IN 12V jack 2 Replace the HOC Refer to part 4 11 3 Connect the new HOC to the system PCB and HOD then other connectors too 4 If normal operation is restored the previous HOC was defective Assemble the system 5 If normal operation is not restored HOD is probably defective Go to PROCEDURE 7 2 29 ...

Page 43: ...to part 4 12 3 Connect the new HOD to the HOC then other connectors too 4 If normal operation is restored the previous HOD was defective Assemble the system 5 If normal operation is not restored system PCB is probably defective System PCB is probably defective Refer to part 2 4 2 30 ...

Page 44: ...whether the keyboard is defective or not The procedures below are outlined in the following pages They should be performed in the order indicated PROCEDURE 1 Input Check PROCEDURE 2 Keyboard Test Execution PROCEDURE 3 Connector Check PROCEDURE 4 New Keyboared Connection 2 31 ...

Page 45: ...r you hit appears on the screen go to PROCEDURE 2 3 If the character does not appear go to PROCEDURE 3 Toshiba Personal Computer MS DOS Version 3 20 I RXXXXX eC Copyright Toshiba C Copyright Microsoft Current date is XXX X XX 19XX Enter new date mm dd yy _ Current time is X XX XX XX Enter new time COMMAND Version 3 20 Corporation 1983 1986 Corporation 1981 1986 A abcdefghijklmnopqrst FIGURE 2 10 K...

Page 46: ...o the FDD and load the test and diagnostics programs Refer to PART 3 2 Run the keyboard test which is indicated in the diagnostics test menu 3 If an error is generated during the test go to PROCEDURE 3 4 If no error is generated during the test the keyboard is normal 2 33 ...

Page 47: ... DC IN l2V ack 2 Remove the top cover assembly Refer to part 4 2 3 Lift the keyboard up and check that the keyboard cable is connected securely to the system PCB If it is connected securely go to PROCEDURE 4 4 If it is not connected securely reconnect it FIGURE 2 11 Keyboard Connector Check 2 34 ...

Page 48: ... l2V jack 2 Remove the keyboard unit Refer to part 4 4 3 Connect the new keyboard to the system PCB 4 If normal operation is restored after connect the keyboard the previous keyboard was defective Assemble the system 5 If normal operation is not restored system PCB is probably defective Refer to part 2 4 2 35 ...

Page 49: ...e outlined in the following pages They should be performed in the order indicated PROCEDURE 1 Display Check PROCEDURE 2 LCD Contrast Check PROCEDURE 3 Display Test Execution PROCEDURE 4 System PCB Connector Check PROCEDURE 5 LCD Module Connector Check PROCEDURE 6 New LCD Cabe Connection PROCEDURE 7 New LCD Module Connection 2 36 ...

Page 50: ... If the message appears go to PROCEDURE 3 4 If the message does not appear first do the following Ca Confirm that tpe contrast knob is adjusted correctly Cb Confirm that the display is not on an external CRT The CRT indicator lamp will be lit if the display is on an external CRT After confirming a and b above perform steps I and 2 again If the message still fails to appear go to PROCEDURE 2 2 37 ...

Page 51: ...then confirm that the screen becomes changed darker or brighter 2 If the screen is changed darker or brighter power supply inputs voltage to the LCD module Go to PROCEDURE 7 3 If the screen is not changed go to PROCEDURE 4 FIGURE 2 12 LCD Contrast Check 2 38 ...

Page 52: ...nostics disk into the FDD and run the test and diagnostics programs 2 If an error is generated during the display test from the diagnostics test menu the system PCB is probably defective Refer to part 2 4 3 If no error is generated the LCD is normal 2 39 ...

Page 53: ... the DC IN l2V jack 2 Remove the top cover assembly Refer to part 4 2 3 Confirm that the LCD cable is connected securely to the system PCB connector PJ 11 4 If the cable is connected securely go to PROCEDURE 5 5 If it is not connected securely reconnect it FIGURE 2 13 System PCB Connector Check 2 40 ...

Page 54: ...pter from the DC IN l2V jack 2 Take out the LCD module Refer to part 4 15 and confi rm that the LCD cable is connected securely to the module 3 If the cable is connected securely go to PROCEDURE 6 4 If the cable is not connected securely reconnect it FIGURE 2 14 LCD Module Connector Check 2 41 ...

Page 55: ...LCD cable to the system PCB and LCD module 2 If normal operation is restored after replacing the LCD module the previous LCD cable was defective Assemble the system 3 If normal operation is not restored LCD module is probably defective Go to PROCEDURE 7 2 42 ...

Page 56: ...able to the system PCB 2 If normal operation is restored after replacing the LCD module the previous LCD module was defective Assemble the system 3 If normal operation is not restored system PCB is probably defective System PCB is probably defective Refer to part 2 4 2 43 ...

Page 57: ...ILITIES 6 SYSTEM CONFIGURATION The test program module is composed of 11 tests as follows 1 SYSTEM TEST 2 MEMORY TEST 3 KEYBOARD TEST 4 DISPLAY TEST 5 FLOPPY DISK TEST 6 PRINTER TEST 7 ASYNC TEST 8 HARD DISK TEST 9 REAL TIMER TEST 10 NDP TEST 11 EXPANSION TEST The following items are necessary for carrying out the test and diagnostic programs 1 T1200 Diagnostics disk 2 MS DOS system disk 3 Work di...

Page 58: ...D UTILITIES 8 SYSTEM CONFIGURATION 9 EXIT TO MS DOS PRESS 1 9 KEY Detailed explanations of the service programs and the operations are given in parts 3 16 to 3 21 4 Press 1 key then Enter The following display will appear TOSHIBA personal computer T1200 DIAGNOSTICS version 1 00 C copyright TOSHIBA Corp 1987 DIAGNOSTIC TEST MENU 1 SYSTEM TEST 2 MEMORY TEST 3 KEYBOARD TEST 4 DISPLAY TEST 5 FLOPPY DI...

Page 59: ... will appear Test drive number select l FDDl 2 FDD2 0 FDDl 2 Media in drivell mode l 360k 2 360k l 2M 720k 3 l 2M 4 720k When select the HARD DISK TEST the following message will appear Test drive number select l HDDl 2 HDD2 0 HDDl 2 5 After pressing the test number 1 to 11 of the DIAGNOSTIC TEST MENU the following display sample will appear TEST NAME SUB TEST PASS COUNT WRITE DATA ADDRESS XX XXXX...

Page 60: ...ror status and stops the execution of the test program The operation guide displays on the right side of the display screen When select the NO When an error occurs it displays the error status then it increments the error counter by one and goes to the next test 8 Type the 1 or 2 then press the Enter The test program will run Each subtest names described in the part 3 3 9 When stop the test progra...

Page 61: ...play page 08 W pattern display 09 Special attribute test 01 Sequential read 02 Sequential readlwrite 5 FDD 03 Randam address data 04 Write specified address 05 Read specified address 0 Ripple pattern 6 PRINTER 02 Function 03 Wraparound 01 Wrap around channel 1 02 Wrap around channel 2 03 Point to point send 7 ASYNC 04 Point to point receive 05 Card modem loopback 06 Card modem on line test 07 Dial...

Page 62: ...itch on After checking the operation of the HOD switch comfirm that signals are being exchange between the CPU and the PS Power Supply Operation for the test is as follows 1 After executing the test the following message will appear HOD off switch test start 2 Turn the HDD switch off The following message will appear HOD off switch test OK 3 Press Enter then return to the subtest menu of the syste...

Page 63: ...original data Subtest 03 RAM refresh Execution time 34 seconds This test writes constant data in 256 bytes length to Memory and then reads and compares it with the or ig inal data The constant data are AAAAHn and II 5555Hn A certain interval time wi 11 be taken between the write and the read operations Subtest 04 Expansion bus Execution time 3 seconds Rote As this test requires a special tool to b...

Page 64: ... the same test as subtest 05 for the EMS memory 384 kbytes page frame address DOOOOH and the block select register 03H This is performed for every 64kbytes Operations for the test is as follows 1 After executing the test the following message will appear Warning The contents of the EMS will be destroyed Press Enter key 2 Press the Enter then the following message will appear EMS port XXXH BLOCK X ...

Page 65: ...e the original state so that it is able to confirm the self repeat function The following three keys are exceptions and each key is changed to the character only when it is pressed and if released it gets back to the original state Ctrl key Shift key Alt key KEYBOARD TEST IN PROGRESS 30100 mmllmammElllmmllllall II III III II 11 1 II II 11 1 III II III III II II 11111 m11111 11 1 II 11 1111 1111111...

Page 66: ...OARD TEST IN PROGRESS 30200 111111 1111 111111 111111 111111 1 II II IF TEST OK PRESS DEL THEN ENTER KEY Subtest 03 Pressed key code display Scan code character code and key top name are displayed on the screen by pressing a certain key as shown below Some keys such as Ins Caps lock Num lock Scroll lock Alt Ctr1 and shift key blink on the screen when each one is pressed Each scan code character co...

Page 67: ... 60 1 02 31 2 03 32 3 04 33 4 05 34 5 06 35 6 07 36 7 08 37 8 09 38 9 OA 39 0 OB 30 OC 20 00 3D 2B 5C OE 08 OF 09 Q 10 71 w 11 77 e 12 65 r 13 72 t 14 74 I 15 79 u 16 75 i 17 69 0 18 6F P 19 70 1A 5B 1B 50 a 1E 61 s 1F 73 d 20 64 f 21 66 9 22 67 h 23 68 j 24 6A k 25 6B I 26 6C 27 3B 3 11 ...

Page 68: ...78 c 2E 63 v 2F 76 b 30 62 n 31 6E m 32 60 33 2C 34 2E I 35 2F Space 39 20 F2 3C 00 F4 3E 00 F6 40 00 F8 42 00 F10 44 00 F1 38 00 F3 3D 00 F5 3F 00 F7 41 00 F9 43 00 Esc 01 18 Home 47 00 48 00 End 4F 00 Uper 48 00 Lower 50 00 PgUp 49 00 40 00 PQDn 51 00 Del 53 00 Sys Req 85 00 PrtSc 37 2A 4A 20 4E 28 3 12 ...

Page 69: ...ing Display In the case of color displays all seven colors used blue red magenta green cyan yellow white are displayed The background and foreground colors can then be checked for brightness The display below appears on the screen when this test is run CHARACTER ATTRIBUTES NEXT LINE SHOWS NORMAL DISPLAY NNNNNNNNNNNNNNNNNNNNNNNN NEXT LINE SHOWS INTENSIFIED DISPLAY I I I I I I I I I I I I I I I I NE...

Page 70: ...ond In this test the shift caracters are displayed in the 80 x 25 pixel mode as shown below 80 25 CHARACTER DISPLAY 012345 78 01234S 78 01236 78 01234S 78 012345678 S L I 01234567 JXYZC l _ bcdet9hijkl_no S L 01234S 7E XYZC J _ bcdet9hijkl_nop S L I 012345678 YZC l _ bcdet9hijklmnopq S L 01234S 78 YZC J bcdet9hijklmnopqr S L 01234S67S ZC l bcd 9hljkl napqr L 01234S 78 1 C J bcd t9hijkl napqr L 012...

Page 71: ...ots graphics mode as shown below 320 200 GRAPHICS DISPLAY PRESS ENTER KEY Subtest 06 640 200 Graphics display Execution time 8 seconds This test displays the color blocks for the black and white display in the 640 x 200 dot graphics mode as shown below 640 200 GRAPHICS DISPLAY EVEN DOTS ODD DOTS DRIVEN DRIVEN PRESS ENTER KEY 3 15 ALL DOTS DRIVEN ...

Page 72: ...HHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH H...

Page 73: ... 1 After executing the test the following message will appear EXT FDD select SW test Change EXT FDD SW OFF Press ENTER KEY Confirm that the above message XXX changes when it is specified by EXT FDD switch 2 After pressing the Enter the following message will appear FONT change test Press Fn key Press ENTER KEY Confirm that the font of the above message cheages by pressing the Fn keys 3 17 ...

Page 74: ...fact that when above combinations of keys are pressed simultaneously the indicator showing the LED status appears on the right of each key group 4 After pressing the Enter the following message will appear Attribute special test 1 FG non zero BG zero R18 bitl O Double 2 FG non zero NE BG non zero Rl8 bit3 2 PRESS ENTER KEY Confirm that the character font changes by pressing Enter 5 After pressing ...

Page 75: ...130 seconds This test writes data to all tracks as defined above continuously and then reads the data out and compares it to original data The data pattern is B5ADADH repeated Subtest 03 Random address data Execution time 12 seconds This test writes random data to random address on all tracks as defined in subtest 01 and then reads the data out and compares it with the original data Subtest 04 wri...

Page 76: ... 0123456789 ttABCDBFGHIJKLMlfOPQRSTUVWXYZ IJ _ bcciefghijklmnopqrstu 0123456789 ttABCDBFGHIJKLMNOPQRSTUVWXYZ V _ abcciefgnijklmnopqr 0123 Q UVWXYZ V _ abcdefghijklmnon abcciefghi 1lr Su test 02 Function Execution time 15 seconds This test prints out various print type as shown below Normal Print Double Width Print Compressed Print Emphasized Print Double Strike Print All Characters Print PRINTBR T...

Page 77: ...as subtest 01 for the channel 2 Subtest 03 Point to point send Execution time 1 second Bote This test can be executed on condition that the both send and receive sides are set in the same condition and also connected together by RS232C direct cable Wiring diagram described in part 3 22 Subtest 03 must be executed together with subtest 04 and vice versa In this test the data 20H to 7EH are sent as ...

Page 78: ...ve side is in the same status as the send side the test cannot be executed Press the Fn SysReq key then confirm that the Built in modem power is on In this test first some data are sent to the modem card from the RS232C inside the system then the data is again sent to the other system through the PBX Private Branch Exchange This test is used whether the returned data from the other system are same...

Page 79: ...nce Execution time 10 minutes This test writes the address data sector by sector track by track then reads the data and compares it to the original data Following three kinds of read operations are performed Forward sequential Reverse sequential Randam Subtest 03 Random address data Execution time 48 seconds This test write random data in random units to random address cylinder head sector and the...

Page 80: ... original data Write specified address Execution time 1 second This test writes specified data to a specified cylinder and head Read specified address Execution time 1 second This test reads data which has been written to a specified cylinder and head ECC circuit CE cylinder Execution time 2 seconds This test checks the ECC Error check and correction circuit functions at the CE cylinder Track 611 ...

Page 81: ... date PRESS ENTER KEY TO EXIT TEST 901000 2 If current date is not correct input the current new date Press the Enter the BDter Dew ti_ message will appear 3 If current time is not correct input the current new time Press the Enter return to the subtest menu of the REAL TIME TEST Subtest 02 Real time carry CA1ft IORI When this test is executed the current data and time is erased This test checks w...

Page 82: ... multiplication functions 3 14 DPAIISIOR UNIT TEST Rote If there is no expansion box connected to the system this test cannot be executed Subtest 01 Box wrap around seconds 8 bits bus Execution time 3 Rote As this test required a special tool to be executed it can not be carried out here Subtest 02 Box mono video ram Execution time 1 second Rote If there is no monochrome display card in the expans...

Page 83: ...removed on dual attach card 08 OMA Overrun Error 09 OMA Boundary Error 10 CRC Error 20 FOC Error 40 SEEK ERROR 60 FDD not drive 80 Time Out Error Not Ready EE Write buffer error RS232C 01 DSR Off Time Out 02 CTS Off Time Out 04 RX EMPTY Time Out 08 TX BUFFER FULL Time Out 10 Parity Error 20 Framing Error 40 Overrun Error 80 Line Status Error 88 Modem Status Error 33 NO CARRIER CARD MODEM 34 ERROR ...

Page 84: ... Drive not initialize 09 DMA Boundary error OA Bad sector error OB Bad track error 10 ECCerror 11 ECC recover enable 20 HOC error 40 Seek error 80 Time out error AA Drive not ready BB Undefined CC Write fault EO Status error FO Not sense error HW code FF NDP 01 NoNDP 02 Control word error 03 Status word error 04 Bus error 05 Addition error 06 Multiplication error 3 28 ...

Page 85: ...See the MS DOS manual for details 3 16 1 Program descriptions 1 All track FORMAT Performs physical shown below Execution time 6 minutes formatting of hard disk in the manner Sector sequences Cylinders Heads Sectors Sector length Bad track unit 3 o to 611 o to 1 lOMbytes o to 3 20Mbytes 1 to 17 512 bytes per sector 10 tracks lOMbytes 20 tracks 20Mbytes 2 Good track PORKaT Execution time 1 second Ex...

Page 86: ...ack FORMAT 4 Bad track CHECK 9 Ex1t to DIAGNOSTICS MENU Press NUMBER key 2 All track PORMA Selection 1 When All track PORMA 1 is selected the following message will appear Interleave number 3 1 9 2 Select an interleave number Usually select 3 Type the number and press Enter The following message will appear Drive nu er select 1 11 2 12 3 Select a drive number Type the drive number and press Enter ...

Page 87: ...ee digits are the cylinder number and the last digit is the head number If the hard disk doesn t have except them press the Enter only This executes the formatting of all tracks 6 After formatting the hard disk the cylinder bead XXX X message will appear then all cylinders of the hard disk are checked If there is a bad track on the hard disk the bad track number will be displayed on the screen 7 F...

Page 88: ...ppear HOD TYPE HOD TYPE HOD TYPE CYLINDER HEAD SECTOR XXX X XX Press Track Number CCCH J key 4 Type a track number four digits and press Enter The first three digits are the cylinder number and the last digit is the head number This executes the formatting of good tracks or bad tracks Ro e This program can format only one track per operation If it is desired to format several good tracks or bad tr...

Page 89: ...Type the dr ive number and press Enter When the following message appears and bad tracks of the hard disk are checked HOD TYPE HOD TYPE HOD TYPE CYLINDER HEAD SECTOR XXX 8 X XX cylinder head XXX X 3 After checking the bad tracks of the hard disk are checked the Po t c lete message will appear 4 Press the Enter to return to the HARD DISK FORMAT menu 3 33 ...

Page 90: ...ENU the following message will appear HEAD CLEANING Mount cleaning disk s on drive s Press any key when ready 2 After the above message appears remove the Diagnostics disk insert the cleaning disk and press any key 3 When the following message appears FDD head cleaning will begin HEAD CLEANING Mount cleaning disk s on drive s Press any key when ready Cleaning start 4 When cleaning is finished the ...

Page 91: ...switch is turned off the error information will be lost The error information itself is displayed as the following 1 Error count eNT 2 Test name TEST 3 Subtest number NAME 4 Pass count PASS 5 Error status STS 6 Address FOO HOD 1 or memory ADOR 7 write data WO 8 Read data RO 9 Error status name This program can store data on a floppy disk or output information to a printer 3 35 ...

Page 92: ...te data Error status name Subtest number Test name Error count 1 Next 2 Prev 3 Ex1t 4 Clear 5 Pr1nt 6 FO LogRead 7 FO LogWr1te 2 Error information to be displayed on the screen can be manupulated with the following key operation The 1 key scrolls the display to the next page The 2 key scrolls the display to the previous page The 3 key returns the display to the DIAGNOSTIC MENU The 4 key erases all...

Page 93: ...g 1 Remove the diagnostics disk and insert the work disk into the floppy disk drive 2 After pressing 6 and Enter to select from the DIAGNOSTIC MENU the following message will appear Printer wrap around test YIN 3 Select whether to execute the printer wraparound test Yes or not No Type the desired Y or N and press Enter key If Y is selected a wraparound connector must be connected to the printer co...

Page 94: ... 15 sectors track c 2BO Two sided high density double track 96 135 TPI MFM mode 512 bytes 15 sectors track 2 COpy This program copies floppy disks Copy with one FDD Drive A Copy with two FDDs Drive A to Drive B 3 DUMP This program display the contents of floppy disks both 3 5 and 5 25 and hard disks designated sectors 3 20 2 Operations 1 After pressing 7 and Enter key to select from the DIAGNOSTIC...

Page 95: ...message will appear Warn1ng D1sk data w1ll be destroyed Insert work d1sk 1n to dr1ve A Press any key when ready 4 Rem0 7e the diagnostics disk frim the FDD and insert the work disk press any key The Po t start message will appear formatting is then executed After the floppy disk is formatted the following messaqe will appear Forwat cOIIPlete Another for at 1 Yes 2 No 5 If you tvpe 1 and press Ente...

Page 96: ...key The Copy started message will then appear After that the following message will appear Insert target disk into drive A Press any key when ready 4 Remove the source disk from the FDD and insert the work disk formatted press any key When coping can not be done with one operation message 2 is displayed again Repeat the operation After the floppy disk has been copied the following message will app...

Page 97: ...rt source disk into drive A Press any key when ready 5 Remove the diagnostics disk from the FDD and insert a source disk press any key The Track Dumber message will then appear Type the track number and press Enter 6 The Bead Daaber message will then appear Type the head number and press Enter 7 The Sector Daaber message will then appear Type the sector number and press Enter The dump list for the...

Page 98: ...rinter port number 7 Co processor number 8 Expanded memory port number 3 21 2 Operations After pressing 8 and Enter key to select from the DIAGNOSTICS MENU the following display will appear SYSTEM CONFIGURATION 640KB MEMORY LCD DISPLAY 1 FLOPPY DISK DRIVE S 1 ASYNC ADAPTOR 1 HARD DISK DRIVE S 1 PRINTER ADAPTOR 0 MATH CO PROCESSOR lEXPANDED MEMORY PRESS ENTER KEY Press Enter key to return to the DI...

Page 99: ...Y 11 6 DATA4 16 INT PRT ACKNOWLEDGE 10 5 DATA3 1 STROBE ERROR 15 FIGURE 3 1 Printer Wrap Around Connector 2 RS232C Wrap around connector 3 TRANSMIT DATA RECEIVE DATA 2 7 REQUEST TO SEND L CLEAR TO SEND 8 1 CARRIER DETECT 4 DATA TERMINAL L DATA SET READY 6 READY RING INDICATE 9 FIGURE 3 2 RS232C Wrap Around Connector 3 43 ...

Page 100: ... RO III TO 3 1 CD III RTS 7 6 OSR OTR 4 8 CTS 9 RI FIGURE 3 3 RS232C Direct Cable 9 pin to 9 pin 4 RS232C direct cable 9 pin to 25 pin 1 CD III RTS 4 2 RO III TO 2 3 TO RO 3 4 OTR CTS 5 OSR 6 RI 22 5 GNO GNO 7 7 RTS CD 8 6 OSR OTR 20 8 CTS 9 RI FIGURE 3 4 RS232C Direct Cable 9 pin to 25 pin 3 44 ...

Page 101: ...l operation etc 2 Only approved tools may be used 3 After deciding the purpose of replacing the unit and the procedures required do not carry out any other procedures which are not absolutely necessary 4 Be sure to turn the POWER switch off before beginning S Be sure to disconnect the ac adapter and all external cables from the system 6 Follow only the fixed standard procedures 7 After replacing a...

Page 102: ...d LCD cover D Rote Replacement procedures for these items are detailed in carts 4 14 to 4 17 ee 1 1 0 FIGURE 4 1 Top Cover Assembly 1 Confirm that the POWER switch is off 2 Turn the unit upside down and remove the seven screws E from the base subassembly F FIGURE 4 2 Removing the Screws from the Base Subassembly 4 2 ...

Page 103: ...attery G by pushing the latch release H to the left and lifting the battery up and out Ci FIGURE 4 3 Removing the Main Battery 4 Remove the two screws I located beneath the main battery FIGURE 4 4 Removing the Screws from the Top Cover Assembly 4 3 ...

Page 104: ...and separated from the base subassembly Once the top cover assembly is separated from the base subassembly it should be stood on its side to the left of the unit FIGURE 4 6 Removing the Top Cover Assembly from the Base Subassembly 7 To reassemble the unit remount the top cover assembly on the base subassembly and follow the above procedures in reverse 4 4 ...

Page 105: ...the top cover assembly as directed in part 4 2 3 Lift the keyboard unit A out and place it in front of the unit 4 Disconnect the LCD cable B from the system PCB C A FIGURE 4 7 Disconnecting the Top Cover Assembly 5 To install a new top cover assembly follow the above procedures in reverse 4 5 ...

Page 106: ...t the keyboard unit out as directed in part 4 2 It is not necessary to remove the keyboard bridge A 3 Release the pressure plate B of connector PJl C to disconnect the keyboard cable from the system PCB FIGURE 4 8 Disconnecting the Keyboard unit 4 To install a new keyboard unit follow the above procedures in reverse 4 6 ...

Page 107: ...nit as directed in part 4 4 3 Remove the single screw A from the memory card 4 To disconnect the memory card cables B press down on the area where the cable is attached to the card and release the pressure plates C then lift the card out 5 Disconnect the two cables D E from the system PCB P 6 Remove the RTC battery G by spreading the plastic latches H 7 Remove the speaker I by pushing the plastic ...

Page 108: ...4 Lift up the keyboard bridge D and disconnect the LED cable E from the system PCB 5 To remove the indicator PCB F from the keyboard br idge remove the single screw G and push the plastic latch H outward pull the top edge I of the indicator PCB upward and outward FIGURE 4 10 Removing the Keyboard Bridge and Indicator PCB G 6 To install a new keyboard bridge and indicator PCB follow the above proce...

Page 109: ...is not necessary to disconnect the keyboard cable and indicator cable 3 Remove the line jack A from its mounting on the back of the FOO base B 4 To remove the built in modem C from the system PCB O remove the ingle screw E At th is time remove the metal FG frame ground from the base subassembly FIGURE 4 11 Removing the Built In Modem 5 To install a new built in modem PCB FLOMDl follow the above pr...

Page 110: ...emove the top cover assembly as directed in part 4 2 3 Disconnect the two forward cables A from the system PCB DO NOT disconnect them from the power supply PCB B 4 Disconnect the remaining three cables C from the power supply PCB C FIGURE 4 12 Disconnecting the Power Supply PCB Cables 4 10 ...

Page 111: ...r supply PCB forward to remove it D FIGURE 4 13 Removing the Power Supply PCB 6 To install a new power supply PCB FLOPS1 follow the above procedures in reverse ROTE The two forward cables A MUST PASS THROUGH the keyboard bridge when connected 4 11 ...

Page 112: ...cted in parts 4 4 and 4 6 It is not necessary to disconnect them 3 Disconnect the expansion bus connector C and remove the line jack D from its mounting on the back of the FDD base E 4 If replacing the FDD base remove the sub battery F from the rear of the FDD base 5 Demount the built in modem G from connector PJ8 and lay it on the system PCB It is not necessary to disconnect it FIGURE 4 14 Discon...

Page 113: ...ently lift the FDD base up and toward the front of the unit At this time remove the HOD mask panel J from the FDD base 8 To remove the expansion bus cable X remove the two screws L from the FDD base H FIGURE 4 15 Removing the FDD Base 9 To install a new FDD base follow the above procedures in reverse 4 13 ...

Page 114: ... directed in part 4 9 3 Remove the three flatheaded countersunk screws A and the FDD GND B from the FDD base 11 _ 8 FIGURE 4 16 Removing the FDD 4 To install a new FDD follow the above procedures in reverse BarB Make sure to place the FDD cable in the location provided for it on the FDD base 4 14 ...

Page 115: ...ted in parts 4 2 4 3 and 4 6 It is not necessary to disconnect them 3 Remove the single screw A and remove the hard disk control PCB B from the system PCB C 4 To remove the hard disk control PCB from the hard disk drive D disconnect the hard disk drive connector E FIGURE 4 17 Removing the Hard Disk Control PCB 4 To install a new hard disk control PCB follow the above procedures in reverse 4 15 ...

Page 116: ... onto a floppy disk before replacing the hard disk This can be done with the MS DOS BACRUP command See the MS DOS manual for details 1 Confirm that the POWER switch is off 2 Turn the un it ups i de down and remove the seven screws A and three flatheaded countersunk screws B from the base subassembly A FIGURE 4 18 Removing the Screws from the Base Subassembly 4 16 ...

Page 117: ...Disconnect the cable C from the hard disk control PCB D and lift the HOD E out FIGURE 4 19 Removing the Hard Disk Dri ve 5 To install a new hard disk drive follow the above procedures in reverse 6 Format the new hard disk with MS DOS FORMAT CIS 4 17 ...

Page 118: ...At this time also remove the mask panel C 4 Disconnect the speaker cable D and RTC battery cable E from the system PCB 5 To remove the system PCB and the memory card from the base subassembly remove the four screws F and lift the system PCB out 6 Remove the memory card from the system PCB as directed in part 4 5 A E FIGURE 4 20 Removing the System PCB 7 To install a new system PCB PCB SET follow t...

Page 119: ...4 14 RBMOnRG RBPLACDIG IftIB LCD MASK 1 Confirm that the POWER switch is off 2 Open the LCD by sliding the two side latches A forward while pulling upward FIGURE 4 21 Opening the LCD 4 19 ...

Page 120: ...A label B and keep it in a clean place 4 Remove the single flatheaded countersunk screw C and take the LCD mask D off by pulling it slightly forward and upward FIGURE 4 22 Removinq the LCD Mask 5 To install a new LCD mask follow t he above procedures in reverse 4 20 ...

Page 121: ...rom the LCD cover subassembly as directed in part 4 14 3 Remove the four screws A on the B FIGURE 4 23 Removing the LCD Screws 4 Disconnect the LCD cable C from the LCD module FIGURE 4 24 Removing and Disconnecting the LCD Module 5 To install a new LCD module follow the above procedures in reverse 4 21 ...

Page 122: ...emove the LCD mask and LCD cover subassembly as directed in parts 4 14 and 4 15 3 Using tweezers or a fine pointed instrument peel off the hinge label A and remove the two screws B that it conceals Keep the label in a clean place FIGURE 4 25 Removing the LCD Cover Subassembly Screws 4 22 ...

Page 123: ...e it from the unit s top cover D FIGURE 4 26 Removing the LCD Cover Subassembly 5 Remove the hinge cover E and the torsion bar F from the top cover FIGURE 4 27 Removing the Hinge Cover and Torsion Bar 6 Replacement procedures are described in part 4 18 4 23 ...

Page 124: ...y seated before proceeding the hooked portion should be positioned vertically B FIGURE 4 28 Inserting the Torsion Bar 3 Insert the short end of the hinge cover plastic cable shield C into the main uni t the torsion bar must be seated in the hinge cover between the cover and the shield The hinge cover itself should be seated on the two pirot ends D D FIGURE 4 29 Seating the Hinge Cover 4 24 ...

Page 125: ...f the hinge cover cable hi ld into the LCD cover seat the LCD cover subassembly under the two dowel ends G FIGURE 4 30 Seating the LCD Cover 7 Rotate the LCD cover assembly to a vertical position while constantly maintaining pressure to prevent separtion of the hinge cover and the LCD cover Insert and tighten down the two LCD cover screws to complete the replacement procedure 8 As directed in part...

Page 126: ...bly C Keyboard bridge D Keyboard unit E Power sup ly PCB F Sub battery G 3 S inch floppy disk drive H I J K L M N 3 S inch hard disk Built in modem Hard disk control System PCB Memory card RTC battery Speaker Base subassembly FIGURE 5 1 Inside the System Unit 5 1 drive PCB ...

Page 127: ...ector 25 pin D shell D Line jack for built in modem E Batery pack F Battery lock G HOD switch 8 DC in jack dc 12 V I Power switch J Expansion slot K EXP FOD connector 25 pin O shell L Key pad connector 2 pin M COMMS connector 9 pin D shell A B e D E F M L K Figure 5 2 Rear Panel 5 2 J ...

Page 128: ...5 1 3 Left side the system unit A Reset switch B A B DIS switch C LCD contrast knob FIGURE 5 3 Left Side the System Unit 5 3 ...

Page 129: ...5 2 SD lBl PCB 5 2 1 System PCB connectors P U B Lll 2 ii FU IO J r c e I Joc D r 36T700966GOI CI J J 0 J OC II Icl D ITCSHIBAI q II I FLONOI c D FIGURE 5 4 System PCB Connectors 5 4 h F E D ...

Page 130: ... H PJ 8 Modem connector I PJ 9 Power supply HDC connector J PJ 10 Expansion bus connector 10 PJ 11 LCD connector L PJ 12 Power supply 5V connector M PJ 13 FDD A connector N PJ 14 FDD B connector 0 PJ 15 I O connector P PJ 16 Power supply signal connector Q PJ 17 Jumper strap HOC R PJ 18 Jumper strap S PJ 19 Jumper strap T PJ 20 Jumper strap Co processor U PJ 21 Jumper strap Font 5 5 ...

Page 131: ...5 2 2 System PCB ICs D E M H FIGURE 5 5 System PCB ICs 5 6 ...

Page 132: ...T FDC F Gate Array Bus driver G Gate Array Bus controller H Gate Array EXP MEM controller I FOC Floppy disk controller TC8565 J ACE AsynchJ onous communication element K PIC Programmable interrupt controller L TIMER 82C54A M DMA Direct memory access 82C37A N KBC Keyboard controller 80C49A 5 7 TC8570 82C59A ...

Page 133: ... 0 STROBE 2 PD01 0 DATA BIT 0 3 PD11 0 DATA BIT 1 4 PD21 0 DATA BIT 2 5 PD31 0 DATA BIT 3 6 PD41 0 DATA BIT 4 7 PD51 0 DATA BIT 5 8 PD61 0 DATA BIT 6 9 PD71 0 DATA BIT 7 10 ACKO I ACKNOWLEDGE 11 BUSY1 I BUSY 12 PE1 I PAPER END 13 SELEC1 I SELECT 14 AUTFDO 0 AUTO FEED 15 ERRORO I ERROR FAULT 16 PINTO 0 PRINTER INITIALIZE 17 SLiNO 0 SELECT INPUT 18 25 GND GROUND 0 V 5 8 ...

Page 134: ... I INDEX 3 TROO I TRACK ZERO 4 WPRO I WRITE PROTECTED 5 RDAO I READ DATA 6 DSKCO I DISK CHANGE 7 9 NOT USED 10 DSELBO 0 DRIVE SELECT 11 MONBO 0 MOTOR ON 12 FDCWDO 0 WRITE DATA 13 FDWEO 0 WRITE ENABLE 14 LOWDNSO 0 LOW DENSITY 15 FSIDEO 0 SIDE SELECT 16 FDIRCO 0 DIRECTION 17 STEPO 0 STEP 18 25 GND GROUND 0 V Note Pin Number 14 is not supported at present but it will be supported in the near futve 5 ...

Page 135: ...TENSITY VIDEO 7 NOT USED 8 CHSY1 0 HORIZONTAL SYNC 9 CVSY1 0 VERTICAL SYNC 5 3 4 COMMS connector 5 PIN 1 2 3 4 5 6 7 8 9 o 00000 0000 6 9 o FIGURE 5 9 COMMS Connector TABLE 5 4 COMMS Connector Signal Names SIGNAL 1 0 DESCRIPTION DCD1 I DATA CARRIER DETECT ROO I RECEIVE DATA SDO 0 SEND DATA DTR1 0 DATA TERMINAL READY GND GROUND 0 V DSR1 I DATA SET READY RTS1 0 REQUEST TO SEND CTS1 I CLEAR TO SEND R...

Page 136: ...MP Connector Signal Names PIN SIGNAL 1 0 DESCRIPTION 1 P26CP 0 COMPOSITE VIDEO 2 GND GROUND iO Vl 5 3 6 Key pad connector FIGURE 5 11 Key Pad Connector TABLE 5 6 Key Pad Connector Signal Names PIN SIGNAL I O DESCRIPTION 1 GND GROUND 0 V 2 TENKEY 1 I O TENKEY 5 11 ...

Page 137: ...16 BIT ADDRESS 41 MEWRO 0 MEMORY WRITE COMMAND A021 0 LOWER 16 BIT ADDRESS 42 XMERDO 0 MEMORY READ COMMAND A031 0 LOWER 16 BIT ADDRESS 43 GND GROUND OV A041 0 LOWER 16 BIT ADDRESS 44 XIOWRO 0 I O WRITE COMMAND A051 0 LOWER 16 BIT ADDRESS 45 XIORDO 0 I O READ COMMAND A061 0 LOWER 16 BIT ADDRESS 46 TCl 0 TERMINAL COUNT A071 0 LOWER 16 BIT ADDRESS 47 CALEl 0 CPU ADDRESS LATCH ENABLE GND GROUND OV 48 ...

Page 138: ... 24 NOT USED NOT USED 25 NOT USED NOT USED 26 NOT USED NOT USED 27 NOT USED NOT USED 28 10ERRO I 1 0 ERROR NOT USED 29 NOT USED GND GROUND OV 30 GND GROUND OV NOT USED 31 NOT USED NOT USED 32 DACK20 0 DMA ACKNOWLEDGE SIGNAL IRQ61 I INTERRUPT REQUEST 33 NOT USED NOT USED 34 NOT USED NOT USED 35 NOT USED NOT USED 36 NOT USED DRQ21 0 DMAREQUEST 37 MDSLO 0 BUILT IN MODEM SELRCT NOT USED 38 NOT USED NO...

Page 139: ...5 DYBOARD LAYOO l 5 4 1 USA version FIGURE 5 12 USA Version 5 14 ...

Page 140: ...5 4 2 England version FIGURE 5 13 England Version 5 15 ...

Page 141: ...5 4 3 German version FIGURE 5 14 German Version 5 16 ...

Page 142: ...5 4 4 France version FIGURE 5 15 France Version 5 17 ...

Page 143: ...5 4 5 Spain version a1n Version FIGURE 5 16 Sp 5 18 ...

Page 144: ...5 4 6 Italy version FIGURE 5 17 Italy Version 5 19 ...

Page 145: ...5 4 7 Scandinavia version FIGURE 5 18 Scandinavia Version 5 20 ...

Page 146: ...5 4 8 Switzerland version FIGURE 5 19 Switzerland Version 5 21 ...

Page 147: ...5 4 9 Keycap number FIGURE 5 20 Keycap Number 5 22 ...

Page 148: ... r e II 3 II 3 C 5 A A r LL TI c s a 0 u 4 JT 4 0 T d t 00 00 b 1 a 0 n r I 5 0 0 5 E U e u a N r F a I 6 6 F V f v a Q g I F JJ 7 f 7 G W g w 0 T U 8 r 8 H X h a 0 x y F 0 1 9 I Y i 00 00 rr 9 9 Y e 0 r r A J Z J z t db n U B c1 K k o 12 I I C 9 L L I I A A dJ co n I I 0 J M m 1 JI 2 I b N Pt IJ d E E A n A F i 0 0 t l A n 1 r1 5 23 ...

Page 149: ...aning of each pin used in this chip are explained in this section together with its detailed definitions 1 Clock generator 2 Command decoder 3 Bus controller 4 8 16 bit controller 5 Wait controller 6 DMA bus controller 7 DMA page register 8 RAM ROM select controller 9 NMI controller 10 Keyboard controller 11 Circuitry compatible with the 8255 80 51 50 100 1 30 FIGURE A I Bus Controller G A A 1 ...

Page 150: ...ffer PortA Buffer KBCL1 KBDTt I I I K B Data s p I I Command S20 oo I Controller L DMAEN IHEO ADOt 1 DMAEN IHEO AD01 OSC141 TEST1 t WaitJDMA Controller 14 JIIIIMHZ I I lJ Bus Controller I L _ Oock 4 Generator 7 MADB1 MEWEO DMESLO RASTHO RASTLO ROMENG ROMCSO NMI1 TMGAT1 SPKDRO KBCLK1 KBDTA1 IRQ11 INTAO MERDO MEWRO IORDO CALEt HLDA1 AOI1 WDLAT WDLENO IWDlR1 IDLENG IWHENG RGTO PAOlO NOY1 DRDY1 CPO IC...

Page 151: ...r byte bus 6 I A13 A131 Address bit 13 7 I A14 A141 Address bit 14 8 I A15 A151 Address line bit 15 9 I O A16 A161 Address line bit 16 10 I O A17 A171 Address line bit 17 11 I O A18 A181 Address line bit 18 12 I O A19 A191 CPU OMA address lines CPU address is input when input mode OMA page register content is output when output mode OMA cycle Address line bit 19 13 0 BOLEN BOLENO Byte bus low enab...

Page 152: ...I S10 CPU status signal bit 1 22 I SOO CPU status signal bit 0 23 1 0 CRGO CRGOO This gate sends a low pulse to RQ GT pin of the CPU when the GA receives a HRQDM 1 signal from the 82C37 Then it sends a HOLDA1 signal to the 82C37 when it receives a low pulse to the CPU from this gate when the DMA cycle is completed 24 0 ROMCS ROMCSO ROM select signal ROM FOOOO FFFFF 25 1 0 BAMCS BAMCSO Back up memo...

Page 153: ...gnal is active high 34 I KBCl KBCl1 Clock signal from the key board controller This is used to transfer data from the keyboard controller 35 I KBDT KBDT1 Data from the keyboard controller 36 I 870N 870N1 8087 installed 37 I INT87 INT871 8087 interactive 38 I KSClK KSClK1 Keyboard status clock 39 I KSDAT KSDAT1 Keyboard status data 40 GND Ground 41 0 KBCLK KBCLK1 Data transfer clock to the keyboard...

Page 154: ...z 46 I TEST1 P03AO Output command inhibit signal 47 I TEST2 P03BO Test mode selection 2 48 I TEST3 P03CO Test mode selection 3 49 I CLR PSRSTO PS reset 50 0 DRQO DRQ01 DMA request for CHO 51 0 IRQ1 IRQ11 Interrupt Request level 1 signal for the keyboard interrupt 52 0 TMGAT TMGAT1 Control signal to the gate 2 of the 82C53 53 Vee 5V 54 0 TMCLK TMCLK1 Clock signal for the 82C53 55 0 CPCKB CPCKB1 CPU...

Page 155: ...quest 61 110 DMER MERDO Memory data read command 62 I DHRQ DHRQ1 DMA hold request signal from the 82C37 63 I DACK3 DACK30 DMA acknowlegde signal for channel 3 64 0 SPKDR SPKDRO Speaker Drive signal 65 GND Ground 66 0 RASTl RASTlO RAS Strobe Timing low signal 67 0 RASTH RASTHO RAS Strobe Timing High signal 68 I DACK2 DACK20 DMA acknowlegde signal for channel 2 69 I PSNMI PSNMI1 Power supply NMI 70 ...

Page 156: ...and 76 I ROY IOROY1 110 ready signal 77 0 DMSL OMSELO V RAM select signal 78 Vcc 5V 79 0 ECRT FLTOSl1 Flat display select signal 80 0 OFNT CHFONTO Double font select signal 81 0 lOOMS 10OMSO 100 Bus memory select signal 82 I MeReS MeReso Machine control register chip select 83 0 BWHEN BWHENO High data odd enable signal for byte to the 1 0 bus 84 0 BWOIR BWOIR1 Specifies data direction Held to be l...

Page 157: ...on to 8 bit bus 90 GNO Ground 91 I OSC SC141 Output from the OSc 14 31818MHz 92 I PPICS PPICSO PPI select signal This signal is active low 93 0 CALE CALE1 CPU address latch enable signal 94 HLOA HlOA1 Hold acknowledge 95 1 0 DO 10001 Bidirectional data bus bit 0 96 1 0 01 10011 Bidirectional data bus bit 1 97 1 0 02 10021 Bidirectional data bus bit 2 98 110 03 10031 Bidirectional data bus bit 3 99...

Page 158: ...er clock 4 77MHz 9 54MHz 4 77MHz Duty 50 1 ISMHz Duty 50 CPU clock rate is changed by selecting one of the two modes Fast Low A 4 2 Command decoder Commands to the I O controller or memory are generated by decoding the CPU status TABLE A 2 Command Decoder Command 52 51 50 0 0 0 INTAO 0 0 1 IORDO 0 1 0 IOWRO 0 1 1 None 1 0 0 MERDO 1 0 1 MERDO 1 1 0 MEWRO 1 1 1 None A 4 3 Bus controller The bus cont...

Page 159: ...as a response to the DMAS request from the DMAC It issues HOLDAl signal to theDMAC when the bus is disconnected then the DMA cycle starts After the DMA cycle is completed it changes the bus connection to the CPU by sending a signal to the RQ GT gate of the CPU A 4 7 DMA Page register This register is to save the upper 4 bits of the address lines A19 A16 during the DMA cycle This is composed of 3 s...

Page 160: ... When the circuitry receives one byte data from keyboard controller it inhibits from receiving more data and issues interrupt signal IRQl A 4 10 Circuitry compatible with 8255 This circuitry is compatible with the intel 8255 PPI chip It contains Port A B A and some control registers a Port A I O address 060H Data setting to the register is performed by writing to the I O address 060H Getting the d...

Page 161: ... Hold keyboard elK low T 7 Enabled keyboard Each bit of the register PC bit after power on reset is as followsJ BIT State c Port C I O address 062H Data setting to the register is performed by writing to the I O address 062H Acquiring the data from the register is performed by reading the same address when bit 0 PCO 3 and bit 3 PC4 7 of the mode control register are set to 0 Bit 0 and 3 of the mod...

Page 162: ...atch data PCO 3 is selected as read data of PCO 3 0 1 SW data is selected as read data of PCO 3 0 PC latch data PC4 7 is selected as read data of PC4 7 3 1 Status information is selected as read data of PC4 7 0 PA latch data is selected as read data of PA 4 1 KB data is selected as read data of PA 0 Not used 7 1 Enable to set mode control register Resets PortA PortB PortC A 14 ...

Page 163: ...altogether and the functions or devices of each controller are as follows a FDD Controller Digital Input Register 3F7H Read Digital Output Register 3F2H Write X Rate Register 3F7H Write DMA Request Delay Write Precompensation FDC Chip Select b Printer Controller Data Register 378H Read Write Status Register 379B Control Register 37AB The detailed explanation about each pin is also given together w...

Page 164: ...t7 IRQ7 Control Register O C I 1 SELINO I rt r PINTO J AUTFDO CK 0 r TRRO r 1 A 5 I EN _ T BUSY 7 o J 1 1 6S s 5 PE o J SELEST EN o J ERROR J2 F SYD7 0 A 1L PRT St tus Re d C COMMAND ADDRESS ____________ 1 DECODER FIGURE B 1 PRT FDD Gate Array Block Diagram B 2 ...

Page 165: ... IRQ5 IRQ51 Interrupt Request 5 signal 12 0 HDCS HDCSO HDC chip select signal 13 0 HDIR HDIR1 Direction of the system data bus towards HDC 14 N C 15 GND Ground 16 N C 17 0 FDRDY FDRDY1 When FDD is selected this signal becomes FDRDY1 that is OR for both of DSLB and DSLA 18 0 DRQ2 DRQ21 DMA request to 82C37 but is suspended 19 0 IRQ6 IRQ61 Interrupt request to 82C59 20 0 TC1 TC1 Output signal invert...

Page 166: ...SYD61 bit6 42 I DACK2 DACK20 Channel 2 Acknowledge signal from DMA 43 0 IRQ7 IRQ71 Interrupt request 7 44 I FINT FDCIT1 Interrupt request from FDC 45 I FDRQ FDCRQ1 DMA request from FDe 46 I CKFD CKFD1 Clock signal from Variable Frecuency Oscillator 47 I FDCWD FDCWD1 Write data signal from FOC 48 I FOCWE FOCWE1 Write enable signal from FOC 49 I PSO PS01 Write precompensation control signal from FDC...

Page 167: ... to FDD 60 0 FDCS FDCCSO Chip select signal to FDC 61 0 FRES FRST1 Reset signal to FDC controlled by DOR bit 2 62 0 MIN MIN1 VFO Variable Frequency Oscillator 63 0 MFMO LOWDO To the MFM FM pins of the VFO 64 0 MFM1 LOWD1 Inverted LOWDO output signal 65 GND Ground 66 0 IDSLA IDSLAO Drive A select signal 67 0 IMONA IMONAO Drive A motor ON signal 68 0 IDSLB IDSLBO Drive B select signal 69 0 IMONB IMO...

Page 168: ...ady to receive the next data this bit is set to 0 for 5ps Normally it is set to 1 87 I PE IPE1 When this bit is set to 1 the printer is in the state of End of paper 88 I SEL ISLCT1 When this bit is set to 1 the printer is in the state of selected 89 I ERR IERRO When this bit is set to 0 the printer is in the state of either Paperend offline orof error 90 GND Ground 91 0 OPD7 0 OPD70 00 Output of d...

Page 169: ...nged This bit is effective only when internal 3 S inch FDD is used and when the external FDD is used this bit is always set to 0 EXTB External FDD B When this bit bit 6 is set to nl the external FDD Sel switch is set to Drive B EXTA External FDD A When this bit bit S is set to nln the external FDD Sel switch is set to Drive B Ext FDD Sel SW EFDSL1 EFDAO Status 1 2 0 1 Ext FDD Off Off 1 1 Ext FDD D...

Page 170: ...now whether the FDD is active or not This is output also to the EMC GA MultipleKer MOJILA MTONAO MONB MTONBO DSL1 Decoder FDSLAO DSLO FDSLBO I n ToEMCG A DSCH FDD EXTBTO EXTA sw DSL FIGURE B 2 FDD General Block Diagram When this bit is nln it indicates that either drive A or B is selected B 8 ...

Page 171: ... are enabled FRST When this bit is 0 the FDC TC8565F is reset DSLI DSLO IDEN When both of these bits are 0 the drive A is selected When DSLI is 0 and OSLO is 1 the drive B is selected When this bit is 1 the following signals are enabled TCO DACK20 DRQ2l IRQ6l B 4 3 X Rate register 3F7H Write Bit 3 2 IRat 1 1 Ra oI 5 J4 6 Not used X Rate 1 X Rate 0 0 0 360rpm 500 kb s MFM 0 1 360rpm 300 kb s MFM 1 ...

Page 172: ...MFM FM LOWD1 INT FDD X EXT FDD FIGURE B 3 Printer FDD Gate Array Write Precompensation Input RS1 RSO 0 0 0 1 1 0 FDCCSO Chip Select FDC Register Data Register Main Status Register Output Write data asitis 12S 1s early 12S 1s late 3FSH 3F4H FDDSLO signal is sent from EMC B 10 ...

Page 173: ...a4 Data3 Data2 Data1 DataO By this register 8 bit write data is set These bits are sent to the printer through the driver LSOS B S 2 Data register input 318H By this register the response data from the printer connector can be read This function is used for wrapround test and is used also for data input from external devices connected to the connector In this case the driver must be set to 0 All t...

Page 174: ...When this bit is set to I IRQ signal from the printer port is output to the 82CS9 PIC PDIR This signal decides the data transfer direction of the 8 bit data on the connector When this bit is set to I input from the connector is enabled and when 0 output from the Data Register is enabled STRB This signal is inverted to be output to the connector AUFD This signal is inverted to be output to the conn...

Page 175: ...signal is used to control the direction of the data to or from the printer port When this bit is set to 0 bit 7 of the control register is disabled and only output from the printer port is enabled Control Register bit 7 Data to the connector Mode Register bit7 I FIGURE B 4 Data Transfer Direction Control B 13 ...

Page 176: ...connected to the I O bus can be selected C 2 FURCTIORS This gate array contains the following functions Latches the CPU address and data Switches the CPU address data and those of the DMA Controls the data transfer between the CPU and the I O bus or the system bus Decodes the I O address Controls the refresh request Contains the back up register for resuming This gate array is composed of 100 pins...

Page 177: ...IAOI9 lIi n t Zj H j c c tz I n I I IX I o o l o I IQ t1 I a IA019 16 IA015 88 19 OA19 16 t LA 15 8 OMA07 0 A19 16 A15 8 A7 0 OMA07 4 OMA03 0 1007 0 SY07 0 w en i elf R o i ...

Page 178: ...ignal During the DMA cycle this signal is active I O data bus enable signal When a device on the I O data bus is accessed this signal becomes active HLDA INTA IODMS HLDA A9 AS OCO OD OES OEF IORD IOWR I O data bus direction signal When this sisgnal is 1 writing operation is enabled and when non reading is enabled INTA IODMS MERD IORD AS A9 YIODEN I O data input output buffer is enabled SYDEN IODIR...

Page 179: ...us from the CPU 12 I RESET RESETO Power on reset signal 13 I lOW 10WRO 110 write command signal 14 I lOR 10RDO 110 read command signal 15 GND Ground 16 0 INTCS INTCSO Interrupt controller chip select signal 17 I BOLEN BDLENO EVEN data enable signal When WDLEN is 0 it is inhibited 18 0 A19 16 A191 161 Upper 4 bits of the address bus and during the DMA 21 cycle they become in the state of high imped...

Page 180: ...1 During the DMA cycle this signal is 2 38 0 CAlE CAlE1 Address AD191 AD001 is latched at the rising edge of the H pulse 39 0 PDICS PDICSO Programmable 1 0 port chip select signal 40 GND Ground 41 I TEST2 P02AO Test pin 42 I WDlEN WDlENO When the word 1 0 is accessed EVEN data is enabled to be latched 43 I WDlAT WDLAT1 When the word 110 is accessed EVEN data is latched 44 0 PAGWR PAGWRO DMA page r...

Page 181: ...SO Memory select signal on the I O data bus 51 0 SYD61 one of the bidirectional8 bit data bus 52 0 A02 A021 Address bit 2 53 Vcc 5Vdc 54 GND Ground 55 0 SYD71 one of the bidirectional 8 bit data bus 56 A10 06 A101 A061 Adress bit 10 6 60 61 I TEST1 P02BO Test pin 62 0 A03 05 A031 A 051 Addressbit3 5 64 65 GND Ground 66 0 SYD01 51 Six of the bidirectional data bus 71 72 0 A12 11 A121 A111 73 Addres...

Page 182: ...the DMA address input 82 from the 82C37 83 0 DMAD61 01 Lower 4 bits of the DMA address input from the 86 82C37 During the CPU cycle CPU address A041 AOB 1 is output to the 82C37 87 0 DMACS DMACSO DMA controller chip select signal 88 I DALE DALE1 DMA address 10071 01 is latched at the leading edge of the H pulse 89 I ADOO AD001 One of the lower 16 bits of the data bus from the CPU 90 GND Ground 91 ...

Page 183: ...OO OIF 020 03F 040 0SF 080 09F OAO OBF 060 07F OEO OE4 Signal name DMACSO INTCSO TIMCSO PAGWRO NMICSO PPICSO MCRCSO In the DMA mode chip select signal should not be output and therefore HLDAI signal must be set to 1 See c s Pin 37 Each signal is described by the logical mode as followsJ DMACSO A9 A8 A7 A6 AS HLDA INTCSO A9 A8 A7 A6 AS HLDA TIMCSO A9 A8 A7 A6 AS HLDA PAGWRO A9 A8 A7 A6 AS IOWO HLDA...

Page 184: ... the contents to be read out TABLE C 2 Index Address and Contents Index Register Contents to be read in the Port OFH 50 82C53 Control Word Register 0 51 n 2 52 82C59 Initialize Command Word 1 53 n 2 54 n 4 I O Back up Index Register I O Back up Data Register OFOH OFlH Both Index register and Data Register are in the clearn status when power is on On writing data the address of the above S register...

Page 185: ...6 o 0 I 9 CD Ek 0 CD I 0 0 g I 0 CD CII 1 D II I ow eo l j 0 s l 0 CII I II a Q o I I CII D oJ OCII 1 0 2 5 L I CD 0 I 9 II ID Q ow 0 6 I oJ o I o FIGURE C 2 Data Register and Index Register C 10 ...

Page 186: ...with the V RAM and with the CG ROM 80 51 50 100 1 30 FIGURE 0 1 Display Conroller Gate Array The detailed description of each pin and signal is also given here The whole system including this gate array is called the Display Controller Subsystem and it can control the following two types of displays A 640x200 dot LCD Liquid Cristal Display B 640x200 dot CRT Cathode Ray Tube Display Note that the e...

Page 187: ...ORD10 10WRO Controller V RAM DMESLO G A Control Address MERDO 100 pin 4 V RAM V MEWRO package 110 IORDY1 RESETO AT71 AT01 8 TEST CC71 CC01 3 8 DUTY1 1 CGAX1 1 1 Latch GQEl 1 QSC141 1 ROM Address QSC171 1 6 V PDPQ 1 Address CEROMO FLTDSL1 1 1 CG ROM CFNQ 1 Out GND 4 CG71 CG01 Vcc 4 9 8 Video IExternal Signals Display L Buffer LCD FIGURE 0 2 Display Controller Subsystem 0 2 ...

Page 188: ...able signal for CG ROM Character generater ROM 8 I CG02 CG21 Character generator output signal bit 2 9 I CG01 CG11 Character generator output signal bit 1 10 I CGOO CG01 Character generator output signal bit O 11 0 RS01 RSA01 Raster scan address bit O 12 0 RS11 RSA 11 Raster scan address bit 1 13 0 RS21 RSA21 Raster scan address bit 2 14 0 RS30 RSA31 Raster scan address bit 3 Not used 15 GND Groun...

Page 189: ...A081 Refresh address bit 08 26 0 RA07 RA071 Refresh address bit 07 27 0 RA06 RA061 Refresh address bit 06 28 I VCC 5V 29 0 RA05 RA05l Refresh address bit 05 30 I OC14 OSC141 Clock 14 31818 MHz for the video signal DIOSLO 31 I ISLO Display 1 0 selected Access signal to the 1 0 port of the GA 32 I MSLO DMESLO V RAM access signal for cpu 33 1 0 BD07 SYD71 Data bus bit 7 34 1 0 BD06 SYD61 Data bus bit...

Page 190: ...A051 CPU address bit 5 45 I UA04 A041 CPU address bit 4 46 I UA03 A031 CPU address bit 3 47 I UA02 A021 CPU address bit 2 48 I UA01 A011 CPU address bit 1 49 I UA14 A141 CPU address bit 14 50 I MEWO MWRO Memory write signal for V RAM write 51 I MERO MROO Memory read signal for V RAM read 10RO IOR01O 52 I I O read signal It read out I O port data to the data bus BOOO B007 53 I VCC 5V IOWR10 54 I 10...

Page 191: ...nal Vertical sync signal for LCD RGB CRT display 64 0 SXV1 SXVD1 Shift clock for LCD 65 0 GND Ground LPHS1 66 0 LHS1 Video signal Horizontal sync signal for LCD RGB CRT display 67 0 DOR1 D1R1 Video signal Red signal for RGB CRT display 68 0 DIG1 D2G1 Video signal Green signal for RGB CRT display 69 0 02B1 D3B1 Video signal Blue signal for RGB CRT display 70 0 D311 0411 Video signal Intensity signa...

Page 192: ...them to V RAM odd address 77 0 CELO CELO Chip enable low It is V RAM selection sIgnal 78 VCC 5V 79 0 RAOO URA001 CPU I Refresh address bit O 80 0 RA01 URA011 CPU I Refresh address bit 1 81 0 RA02 URA021 CPU I Refresh address bit 2 82 0 RA03 URA031 CPU I Refresh address bit 3 83 0 RA04 URA041 CPU I Refresh address bit 4 84 I O ATOO AT01 Attribute data bit O 85 I O AT01 AT11 Attribute data bit 1 86 ...

Page 193: ...ibute data bit 7 CCOO CC01 93 1 0 Character code data bit o CCOl CCll 94 1 0 Character code data bit 1 CC02 CC21 95 I O Character code data bit 2 CC03 CC31 96 I O Character code data bit 3 04 41 97 1 0 Character code data bit 4 COS CC51 98 1 0 Character code data bit 5 CC06 CC61 99 I O Character code data bit 6 C07 CC71 100 1 0 Character code data bit 7 0 8 ...

Page 194: ...M 8 K bytes 64 K ROMx1 OSC CPU ClK 14 31818 MHz Others Multiplexer 74 HC 157x2 latch 74 HC 273x1 Display Buffer The following table shows the operation modes of the DCS of the internal LCD and external CRT display TABLE D 3 LCD CRT Operation Mode Operation lCD CRT lCD CRT Resolution Character Box Mode Pixels Pixels 40 x 25 TEXT 320 x 200 8x8 80 x 25 TEXT 640 x 200 8x8 320 x 200 320 x 200 8x8 GRAPH...

Page 195: ...ignal is low and DIOSLO is also low the data of the I O port is transferred to the CPU through the bus BOOO BD07 IOWRO I O Write Input When this signal is low and OIOSLO is also low the data from the CPU is written to the selected I O port inside the gate array through the bus BOOO B007 DMESLO Display Memory Selected Input When this signal is low the CPU or OMAC is enabled to access the video RAM ...

Page 196: ...o the V RAM IOROYI I O Ready Output When access requirement to the V RAM is generated from the CPU or OMAC if OMESLO becomes low the gate array keeps this signal at low level and puts the CPU and OMAC in the waiting position until the access is enabled RSTO RESETO Reset When this signal is at low the gate array is reset 0 S 2 V RAM signals 34 lines UROO UR04 CPU Refresh Address 00 04 Input RAOS RA...

Page 197: ...the bus BOOO B007 and when UAOO is at high level one byte of the ATOO AT07 is output to the I O bus BDOO B007 When the CPU or the OMAC writes to the V RAM two bytes of the RAM is enabled but only one of those two RAMs executes the write operation WRCO write Character Code Output WR O write Attribute Data Output These are the write enable signals to the V RAM When the chip enable signal is low and ...

Page 198: ...A06 MA06 ADOS RAOS1 A06 MAOS MAOS AD04 RA041 AOS MA04 MA04 AD03 RA031 A04 MA03 MA03 AD02 RA021 A03 MA02 MA02 AD01 RA011 A02 MA01 MA01 ADOO RAOO1 A01 MAOO MAOO WE WRCCO AOO WRATO Note AOO A14 are address signals from the I O bus of the cpu MAOO MA13 are refresh memory address They are generated by the 6845 circuit or its equivalent inside the gate array RSAO RSAI are raster scan address They are ge...

Page 199: ...V RAM Control Signals TC5565 8 1 0 I I CC71 CC01 WRCCO WE r C CE TC5565 8 1 0 AT71 AT01 WRATO l c WE I C CE CELO FIGURE 0 3 V RAM Control Signals o 14 ...

Page 200: ...e codes in the TEXT mode 0 5 3 Character generator CG signals 16 lines CGAI CG Address Latch Output This signal is used to set the character code read out from the V RAM in the external latch The set timing of the external latch circuit is at the raising edge of this signal The output from the external latch circuit is used for the address of the CG ROM As the character code is of 8 bit it can sel...

Page 201: ...s used to select either single dot character or double dot character font INTEN1 Low Single dot character INTEN1 high Double dot character RSA01 RSA21 and RSA31 are raster scan address The RSA01 is the lowest bit LSB TABLE 0 5 ROM Address Assignment RSA31 RSA21 RSA11 RSA01 L L L 0 N L L H 1 8x8 0 T L H L 2 Character L H H 3 U H H L 4 S E H H H 5 0 H H L 6 H H H 7 III 1 byte D 16 ...

Page 202: ...gnals 3 lines CHFONTO Chanqe Character Font Input Composite CMPl CMPl CMPl CMPl CMPl CMPl This signal is to change the font displayed on the screen The function of this signal is shown on the Table 0 7 FLTDSLI Flat Display Selected Input This signal is to select one of internal and external display unit If this signal is at high level the internal LCD is selected If this signal is at low level the...

Page 203: ...or 14 MHZ Input This clock is the input signal to generate a video signal for the CRT display The frequency of the clock must be l4 3l818MHZ OSC17l Oscillator l7 SMHz Input This clock is the input signal to generate a video signal for the plasma display The frequency of the clock must be l7 SMHZ 0 5 7 Other signals 5 lines DGDISI GA Off Input If this signal is at high level the gate array is disab...

Page 204: ...tes 128 pages and as one system can control up to four EM units the whole system can have maximum 8 Mbyte space All of this is possible in theory but in fact as there is a limit in the real installation the maximum 384 kbyte address space is provided as its standard mode I O ports used for the EM unit are 2X8H 2XFH and different I O por is assigned for each unit X can be any of the numbers 0 1 5 6...

Page 205: ...F 00 EFFFF System Memory 640 kbytes EM Expanded Memory Unit Expanded Memory Page 0 Page 1 Page Register Page 2 16kbytes Page 3 16 kbytes 16kbytes 16 kbytes Page 23 1 page 16 kbytes In the T1200 system max 384 kbyt of the memory space is provided FIGURE E l Memory Assignment for the EMU E 2 e ...

Page 206: ...address 14 15 GND Ground 16 0 DRA01 Memory ROW COL address 17 0 IRQ4 IRQ41 Interrupt request 4 18 0 IRQ3 IRQ31 Interrupt request 3 19 0 CMCK1 DACKOO Communication Clock refresh Expansion Interface 20 0 MDSLO IRQ41 When the modem card is used modem select signal and when I F interrupt request 4 21 I SPTON SPTONO Speaker drive signal 22 0 BRDIS BRDIS1 Back up RAM disable signal 23 0 BMDSL BMDSLO Bui...

Page 207: ... 36 I RASTH RASTHO RAS timing high AOO ODD 37 I RASTL RASTLO RAS timing low AOO EVEN 38 I SPKDR SPKDRO Speaker drive signal 39 I RFSTR RFSTR1 Refresh start signal 40 GND Ground 41 0 SPK SPK1 Speaker on signal 42 0 R232CS R232CSO RS232C select 43 0 RTCCS RTCCSO RTC select 44 0 RTCRO RTCROO RTC real command 45 0 RTCWR RTCWO RTC write command 46 I BMIRQ BMIRQO Built in modem interrupt request 47 TEST...

Page 208: ...a Normally inverted data is output 60 0 PRTSl PRTSlO Printer select signal 61 I CEl CElO V RAM chip enable signal 62 I AOO AOB 1 System address 63 I DACKO DACKO Memory refresh signal 64 0 FDDSl FDDSlO FDD select signal 65 GND Ground 66 0 DGDIS DGDIS1 Display GA disable 67 I lOR 10RDO I O read When this is low data is output 68 I lOW 10WRO I O write 69 I RESET RESETO System address bus 70 I A19 15 ...

Page 209: ... A041 System address bus 81 0 DIOSL DIOSLO Display select signal 82 A06 I A061 System address bus 88 A12 89 I DO SYD01 System address bus 90 GND Ground 91 I D1 D7 SYD11 SYD71 System address bus 97 98 0 RAS2H RAS2HO Memory RAS timing 99 0 RAS2L RAS2LO Memory RAS timing 100 I AOS AOS1 System address bus E 6 ...

Page 210: ... Definition of these two registers are as follows TABLE E 2 Index Data Registers and Bit Assignment of the EMC Register I Index Address Data Register Write Read 50 EM Conf Reg 0 of EM 51 EM Conf Reg 1 of Write Read EM bit 7 EMU 10 bit 3 6 2 Conf 1 Reg O 5 0 4 3 EMU Port bit 3 of 2 2 of 1 1 of 0 0 of bit 7 Block SEL2 EM Block SEL 1 Conf 6 Block SELO Reg 1 5 of 4 Hard RAM bit 4 of 3 3 2 2 1 1 0 0 No...

Page 211: ...am except BIOS E 6 Ell CmlPIGORA l ION REGIS l ER 0 Index 50 0 E 6 I Wr i te Within thi register I O address of the EM unit is set by the bits 3 0 of the EMU port while bits 7 4 are not used Bit 1 0 Address 3 2 1 0 When Power is on 0 0 0 0 208H 20FH 0 0 0 1 218H 21FH 0 1 0 1 258H 25FH 0 1 1 0 268H 26FH 1 0 1 0 2A8H 2AFH 1 0 1 1 2B8H 2BFH 1 1 1 0 2E8H 2EFH X 1 1 1 Disable Note Disable Read Write op...

Page 212: ...ts 4 0 Hard RAM bits 4 0 These are the bits used when expansion memory is used as the Hard RAM The expansion memory with the following capacity is used as the Hard RAM Bit Real memory capacity 4 3 2 1 0 of the EM 0 0 0 0 0 0 0 0 0 0 1 64 kbytes 4 pages 0 0 0 1 0 128 kbytes 8 pages S S S S S S 1 1 1 1 1 2 Mbytes 128 pages These bits 4 0 are not used as hardware of the EM but as software RMM SYS BIO...

Page 213: ...00 C8000 ccooo 03FFF 07FFF CBFFF CFFFF 2 0 1 0 00000 04000 08000 ccooo 03FFF 07FFF OBFFF CFFFF 3 0 1 1 00000 04000 08000 ocooo 03FFF D7FFF DBFFF DFFFF 4 1 0 0 EOOOO 04000 08000 DCOOO E3FFF 07FFF DBFFF DFFFF 5 1 0 1 EOOOO E4000 D8000 ocooo E3FFF E7FFF DBFFF OFFFF 6 1 1 0 EOOOO E4000 E8000 DCOOO E3FFF E7FFF EBFFF DFFFF 7 1 1 1 EOOOO E4000 E8000 ECOOO E3FFF E7FFF EBFFF EFFFF E 10 ...

Search results

Summary of Contents for T-Series T1200

Reviews:

Related manuals for T-Series T1200

Brands by name

Popular brands

Toshiba T-Series T1200, User Manual

Search results

Summary of Contents for T-Series T1200

Reviews:

Related manuals for T-Series T1200

Brands by name

Popular brands