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SD-R5112 Rev.1.0
6.2.2. Timing of Host Interface (PIO)
Figure 10 shows the Host Interface Timings.
Address valid*1
DIOR-/DIOW-
Write data valid*2
Read data valid*2
IOCS16-
IORDY
t4
t6
t7
t9
tA
t8
t1
t5
tB
tRD
t6Z
*1:Device Address consists of signals CS0-, CS1-, and DA2-0
*2:Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)
t0
t2
t3
t2i
PIO timing parameters min (ns) max (ns)
Min Time (ns)
Max Time (ns)
t0
Cycle time
120
t1
Address valid to DIOR/DIOW-setup
25
t2
DIOR/DIOW-pulse wide
70
t2i
DIOR/DIOW-recovery time
25
t3
DIOW-data setup
20
t4
DIOW-data hold
10
t5
DIOR-data setup
20
t6
DIOR-data hold
5
t6Z
DIOR-data tristate
30
t7
Addr valid to IOCS 16-assertion
30
t8
Addr valid to IOCS 16-negation
30
t9
DIOR/DIOW-to address valid hold
10
tRD
Read Data Valid to IORDY active
0
tA
IORDY setup time
35
tB
IORDY pulse wide
1250
Figure 10 Host Interface Timing
