4. BLOCK DIAGRAM
4-1. MPEG & SYSTEM Block Diagram
Fig. 4-4-1
ZR35100-PQCG
ENCORDER
BA7607
BA7653
WM8776
<BGA>
ZR35162-BGCG
ISO I/F HOST I/F
1394
128M SDRAM
128M SDRAM
128M SDRAM
128M SDRAM
32M FLASH
Main Cpu(Decorder)
ZR36750-BGCG-V
WM8776
HDMI
Driver
TUNER
EEPROM
FRONT
AN5832
32M CLOCK
32M CLOCK
27MHZ
Digital Video Output
SBREQ
SBDAT
SBVALID
SBCLK
SERIAL BITSTREAM OUTPUT
Video
Audio
Digital Audio Out
Y/C Out
Y/U/V Out
CV BS Out
Digital Video I/F
HDMI Out
SPD IF
ADCMCLK
ADCBLCK
ADCLRCK
DOUT
TV-CVBS
L/R IN
L/R IN
L/R IN
TV
REAR
FRONT
FRONT
Video
Y/C
Video
Y/C
REAR
SW ADC
FR .Y/C IN
CVBS IN
Digital Audio I/F
DAC
L OUT
R OUT
CVBS
SIF
IC502
IC503
IC504
IC505
IC507
IC511
IC506
IC517
IC518
IC513 1/2
IC513 2/2
IC516
IC510
U24
U301
IC509
JC101
J503
SPI
DV INPUT
<BGA>
I C
2
TV
TV
L
R
: : :
ZR35162
RF In
CV BS
Y/C
Y/U/V OUT
J501
J502
DAV-WR532
4558
IC514
SPDIF-OPTICAL
J504
TV CVBS
AFC OUT
